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October 2002
s
SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
s
STORAGE REGISTER CAPABILITY -
MASTER CLEAR
s
CAN FUNCTION AS DEMULTIPLEXER
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4724B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4724B, an 8-bit addressable latch, is a
serial-input, parallel output storage register that
can perform a variety of functions. Data is input to
a particular bit in the latch when the bit is
addressed (by means of input A0, A1, A2) and
when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously read
independent of WRITE DISABLE and address
inputs. A master RESET input is available, which
resets all bits to a logic "0" level when RESET and
WRITE DISABLE are at a high level. When
RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8
demultiplexer; the bit that is addressed has an
active output which follows the data input, while all
unaddressed bits are held to a logic "0" level.
HCF4724B
8 BIT ADDRESSABLE LATCH
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4724BEY
SOP
HCF4724BM1
HCF4724M013TR
DIP
SOP
HCF4724B
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IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE
D: The level at the data input ; Q
i0
The level before the indicated steady state input conditions were established, (i=0, 1,...7)
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3
A0 to A2
Address Inputs
4, 5, 6, 7, 9,
10, 11, 12
Q0 to Q7
Latch Outputs
13
DATA
Data Inputs
15
RESET
Reset Input
14
WRITE
DISABLE
Write Disable Input
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
SELECT INPUTS
LATCH ADDRESSED
C
B
A
L
L
L
Q0
L
L
H
Q1
L
H
L
Q2
L
H
H
Q3
H
L
L
Q4
H
L
H
Q5
H
H
L
Q6
H
H
H
Q7
INPUTS
OUTPUTS OF
ADDRESSED
LATCH
EACH OTHER
OUTPUT
FUNCTION
WRITE DISABLE
RESET
L
L
D
Qi0
ADDRESSABLE LATCH
L
H
Qi0
Qi0
MEMORY
H
L
D
L
DEMULTIPLEXER
H
H
L
L
CLEAR ALL BITS TO "0"
HCF4724B
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
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