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Электронный компонент: L4975

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L4975A
5A SWITCHING REGULATOR
5A OUTPUT CURRENT
5.1V TO 40V OUTPUT VOLTAGE RANGE
0 TO 90% DUTY CYCLE RANGE
INTERNAL FEED-FORWARD LINE REGULA-
TION
INTERNAL CURRENT LIMITING
PRECISE 5.1V
2% ON CHIP REFERENCE
RESET AND POWER FAIL FUNCTIONS
SOFT START
INPUT/OUTPUT SYNC PIN
UNDER VOLTAGE LOCK OUT WITH HYS-
TERETIC TURN-ON
PWM LATCH FOR SINGLE PULSE PER PE-
RIOD
VERY HIGH EFFICIENCY
SWITCHING FREQUENCY UP TO 500KHz
THERMAL SHUTDOWN
CONTINUOUS MODE OPERATION
DESCRIPTION
The L4975A is a stepdown monolithic power
switching regulator delivering 5A at a voltage vari-
able from 5.1 to 40V.
Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
efficiency and very fast switching times. Features
of the L4975A include reset and power fail for mi-
croprocessors, feed forward line regulation, soft
start, limiting current and thermal protection. The
device is mounted in a 15-lead multiwatt plastic
power package and requires few external compo-
nents. Efficient operation at switching frequencies
up to 500KHz allows reduction in the size and
cost of external filter components.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
June 2000
BLOCK DIAGRAM
Multiwatt15V
ORDERING NUMBER: L4975A
MULTIPOWER BCD TECHNOLOGY
1/21
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
9
Input Voltage
55
V
V
9
Input Operating Voltage
50
V
V
7
Output DC Voltage
Output Peak Voltage at t = 0.1
s f = 200KHz
-1
-7
V
V
I
7
Maximum Output Current
Internally Limited
V
6
Bootstrap Voltage
Bootstrap Operating Voltage
65
V
9
+ 15
V
V
V
3
, V
12
Input Voltage at Pins 3, 12
12
V
V
4
Reset Output Voltage
50
V
I
4
Reset Output Sink Current
50
mA
V
5
, V
10,
V
11,
V
13
Input Voltage at Pin 5, 10, 11, 13
7
V
I
5
Reset Delay Sink Current
30
mA
I
10
Error Amplifier Output Sink Current
1
A
I
12
Soft Start Sink Current
30
mA
P
tot
Total Power Dissipation at T
case
< 120
C
30
W
T
j
, T
stg
Junction and Storage Temperature
-40 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-case
R
th j-amb
Thermal Resistance Junction-case
max
Thermal Resistance Junction-ambient
max
1
35
C/W
C/W
L4975A
2/21
CIRCUIT OPERATION (refer to the block dia-
gram)
The L4975A is a 5A monolithic stepdown switching
regulator working in continuous mode realized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMOS power
transistors plus mixed CMOS/Bipolar transistors.
The device can deliver 5A at an output voltage
adjustable from 5.1V to 40V, and contains diag-
nostic and control functions that make it particu-
larly suitable for microprocessor based systems.
BLOCK DIAGRAM
The block diagram shows the DMOS power tran-
sistor and the PWM control loop. Integrated func-
tions include a reference voltage trimmed to 5.1V
2%, soft start, undervoltage lockout, oscillator
with feedforward control, pulse by pulse current
limit, thermal shutdown and finally the reset and
power fail circuit. The reset and power fail circuit
provides an output signal for a microprocessor in-
dicating the status of the system.
Device turn on is around 11V with a typical 1V
hysteresis, this threshold provides a correct volt-
age for the driving stage of the DMOS gate and
the hysteresis prevents instabilities.
An external bootstrap capacitor charged to 12V
by an internal voltage reference is needed to pro-
vide correct gate drive to the power DMOS. The
driving circuit is able to source and sink peak cur-
rents of around 0.5A to the gate of the DMOS
transistor. A typical switching time of the current
in the DMOS transistor is 50ns. Due to the fast
commutation switching frequencies up to 500kHz
are possible.
The PWM control loop consists of a sawtooth os-
cillator, error amplifier, comparator, latch and the
output stage. An error signal is produced by com-
paring the output voltage with the precise 5.1V
2% on chip reference. This error signal is then
compared with the sawtooth oscillator, in order to
generate a fixed frequency pulse width modulated
drive for the output stage. A PWM latch is in-
cluded to eliminate multiple pulsing within a pe-
riod even in noisy environments. The gain and
PIN FUNCTIONS
N
o
Name
Function
1
OSCILLATOR
R
osc
. External resistor connected to ground determines the constant charging
current of C
osc
.
2
OSCILLATOR
C
osc
. External capacitor connected to ground determines (with R
osc
) the
switching frequency.
3
RESET INPUT
Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a
divider to the input for power fail function. It must be connected to the pin 14 an
external 30K
resistor when power fail signal not required.
4
RESET OUT
Open Collector Reset/power Fail Signal Output. This output is high when the
supply and the output voltages are safe.
5
RESET DELAY
A C
d
capacitor connected between this terminal and ground determines the
reset signal delay time.
6
BOOTSTRAP
A C
boot
capacitor connected between this terminal and the output allows to
drive properly the internal D-MOS transistor.
7
OUTPUT
Regulator Output.
8
GROUND
Common Ground Terminal
9
SUPPLY VOLTAGE
Unregulated Input Voltage.
10
FREQUENCY
COMPENSATION
A series RC network connected between this terminal and ground determines
the regulation loop gain characteristics.
11
FEEDBACK INPUT
The Feedback Terminal of the Regulation Loop. The output is connected
directly to this terminal for 5.1V operation; It is connected via a divider for higher
voltages.
12
SOFT START
Soft Start Time Constant. A capacitor is connected between thi sterminal and
ground to define the soft start time constant.
13
SYNC INPUT
Multiple L4975A are synchronized by connecting pin 13 inputs together or via
an external syncr. pulse.
14
V
ref
5.1V V
ref
Device Reference Voltage.
15
V
start
Internal Start-up Circuit to Drive the Power Stage.
L4975A
3/21
Figure 1: Feedforward Waveform
Figure 3: Limiting Current Function
Figure 2: Soft Start Function
L4975A
4/21
stability of the loop can be adjusted by an exter-
nal RC network connected to the output of the er-
ror amplifier. A voltage feedforward control has
been added to the oscillator, this maintains supe-
rior line regulation over a wide input voltage
range. Closing the loop directly gives an output
voltage of 5.1V, higher voltages are obtained by
inserting a voltage divider.
At turn on output overcurrents are prevented by
the soft start function (fig. 2). The error amplifier is
initially clamped by an external capacitor Css and
allowed to rise linearly under the charge of an in-
ternal constant current source.
Output overload protection is provided by a cur-
rent limit circuit (fig. 3). The load current is sensed
by an internal metal resistor connected to a com-
parator. When the load current exceeds a preset
threshold the output of the comparator sets a flip
flop which turns off the power DMOS. The next
clock pulse, from an internal 40kHz oscillator will
reset the flip flop and the power DMOS will again
conduct. This current protection method, ensures
a constant current output when the system is
overloaded or short circuited and limits the
switching frequency, in this condition, to 40kHz.
The Reset and Power fail circuitry (fig 4) gener-
ates an output signal when the supply voltage ex-
ceeds a threshold programmed by an external
voltage divider. The reset signal, is generated
with a delay time programmed by an external ca-
pacitor on the delay pin. When the supply voltage
falls below the threshold or the output voltage
goes below 5V the reset output goes low immedi-
ately. The reset output is an open collector-drain.
Fig 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage
is not yet 5V.
Fig 4B shows the case when the output is 5.1V
but the supply voltage is not yet higher than the
fixed threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150
C and has an hysterysis to prevent unstable
conditions.
Figure 4: Reset and Power Fail Functions.
A
B
L4975A
5/21
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T
j
= 25
C, V
i
= 35V, R
4
= 16K
,
C
9
= 2.2nF, f
SW
= 200KHz typ, unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
i
input Voltage Range (pin 9)
V
o
= V
ref
to 40V
I
o
= 5A
15
50
V
5
V
o
Output Votage
V
i
= 15V to 50V
I
o
= 3A; V
o
= V
re
f
5
5.1
5.2
V
5
V
o
Line Regulation
V
i
= 15V to 50V
I
o
= 2A; V
o
= V
re
f
12
30
mV
5
V
o
Load Regulation
V
o
= V
ref
I
o
= 2A to 4A
I
o
= 1A to 5A
10
20
30
50
mV
mV
5
V
d
Dropout Voltage Between
Pin 9 and 7
I
o
= 3A
I
o
= 5A
0.4
0.55
0.6
0.8
V
V
5
I
7L
Max. Limiting Current
V
i
= 15 to 50V
V
o
= V
ref
to 40V
5.5
6.5
7.5
A
5
Efficiency
I
o
= 3A
V
o
= V
ref
V
o
= 12V
70
75
80
%
%
5
I
o
= 5A
V
o
= V
ref
V
o
= 12V
80
85
92
%
%
5
SVR
Supply Voltage Ripple
Reject.
V
i
= 2VRMS; I
o
= 3A
f = 100Hz; V
o
= V
ref
56
60
dB
5
f
Switching Frequency
180
200
220
KHz
5
f
V
i
Voltage Stability of
Swiching Frequency
V
i
= 15V to 45V
2
6
%
5
f
T
j
Temperature Stability of
Swiching Frequency
T
j
= 0 to 125
C
1
%
5
f
max
Maximum Operating
Switching Frequency
V
o
= V
ref
; R
4
= 10K
I
o
= 5A; C
9
= 1nF
500
KHz
5
V
ref
SECTION (pin 14)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
14
Reference Voltage
5
5.1
5.2
V
7
V
14
Line Regulation
V
i
= 15V to 50V
10
25
mV
7
V
14
Load Regulation
I
14
= 0 to 1mA
20
40
mV
7
V
14
T
Average Temperature
Coefficient Reference
Voltage
T
j
= 0
C to 125
C
0.4
mV/
C
7
I
14 short
Short Circuit Current Limit
V
14
= 0
70
mA
7
V
START
SECTION (pin 15)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
15
Reference Voltage
11.4
12
12.6
V
7
V
15
Line Regulation
V
i
= 15 to 50V
0.6
1.4
V
7
V
15
Load Regulation
I
15
= 0 to 1mA
50
200
mV
7
I
15 short
Short Circuit Current Limit
V
15
= 0V
80
mA
7
L4975A
6/21
ELECTRICAL CHARACTERISTICS (continued)
DC CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
9o n
Turn-on Threshold
10
11
12
V
7A
V
9 Hyst
Turn-off Hysteresys
1
V
7A
I
9Q
Quiescent Current
V
12
= 0; S1 = D
13
19
mA
7A
I
9OQ
Operating Supply Current
V
12
= 0; S1 = C; S2 = B
16
23
mA
7A
I
7L
Out Leak Current
V
i
= 55V; S3 = A; V
12
= 0
2
mA
7A
SOFT START
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
I
12
Soft Start Source Current
V
12
= 3V; V
11
= 0V
70
100
130
A
7B
V
12
Output Saturation Voltage
I
12
= 20mA; V
9
= 10V
I
12
= 200
A; V
9
= 10V
1
0.7
V
V
7B
7B
ERROR AMPLIFIER
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
10H
High Level Out Voltage
I
10
= -100
A; S1 = C
V
11
= 4.7V
6
V
7C
V
10 L
Low Level Out Voltage
I
10
= +100
A; S1 = C
V
11
= 5.3V;
1.2
V
7C
I
10 H
Source Output Current
V
10
= 1V; S1 = E
V
11
= 4.7V
100
150
A
7C
I
10L
Sink Output Current
V
10
= 6V; S1 = D
V
11
= 5.3V
100
150
A
7C
I
11
Input Bias Current
R
S
= 10K
0.4
3
A
G
V
DC Open Loop Gain
V
VCM
= 4V;
R
S
= 10
60
dB
SVR
Supply Voltage Rejection
15 < V
i
< 50V;
R
S
= 10
60
80
dB
V
OS
Input Offset Voltage
R
S
= 50
2
10
mV
RAMP GENERATOR (pin 2)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
2
Ramp Valley
S1 = C; S2 = B
1.2
1.5
V
7A
V
2
Ramp Peak
S1 = C
V
i
= 15V
S2 = B
V
i
= 45V
2.5
5.5
V
V
7A
7A
I
2
Min. Ramp Current
S1 = A; I
1
= 100
A
270
300
A
7A
I
2
Max. Ramp Current
S1 = A; I1 = 1mA
2.4
2.7
mA
7A
SYNC FUNCTION (pin 13)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
13
Low Input Voltage
V
i
= 15V to 50V; V
12
= 0;
S1 = C; S2 = B; S4 = B
0.3
0.9
V
7A
V
13
High Input voltage
V
12
= 0;
S1 = C; S2 = B; S4 = B
3.5
5.5
V
7A
I
13L
Sync Input Current with
Low Input Voltage
V
2
= V
13
= 0.9V; S4 = A;
S1 = C; S2 = B
0.4
mA
7A
I
13 H
Input Current with High
Input Voltage
V
13
= 3.5V; S4 = A;
S1 = C; S2 = B
2
mA
7A
V
13
Output Amplitude
4
5
V
t
W
Output Pulse Width
V
thr
= 2.5V
0.3
0.5
0.8
s
L4975A
7/21
ELECTRICAL CHARACTERISTICS (continued)
RESET AND POWER FAIL FUNCTIONS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Fig.
V
11R
Rising Threshold Voltage
(pin 11)
V
i
= 15 to 50V
V
3
= 5.3V
V
ref
120
V
ref
100
V
ref
80
V
mV
7D
V
11F
Falling Threshold Voltage
(pin 11)
Vi = 15 to 50V
V
3
= 5.3V
4.77
V
ref
200
V
ref
160
V
mV
7D
V
5H
Delay High Threshold
Voltage
V
i
= 15 to 50V
V
11
= V
14
4.95
5.1
5.25
V
7D
V
5L
Delay Low Threshold
Voltage
Vi = 15 to 50V
V
11
= V
14
V
3
= 5.3V
1
1.1
1.2
V
7D
I
5SO
Delay Source Current
V
3
= 5.3V; V
5
= 3V
40
60
80
A
7D
I
5SI
Delay Sink Current
V
3
= 4.7V; V
5
= 3V
10
mA
7D
V
4S
Out Saturation Voltage
I
4
= 15mA; S1 = B
V
3
= 4.7V
0.4
V
7D
I
4
Output Leak Current
V
4
= 50V; S1 = A
V
3
= 5.3V
100
A
7D
V
3R
Rising Threshold Voltage
V
11
= V
14
4.95
5.1
5.25
V
7D
V
3H
Hysteresys
0.4
0.5
0.6
V
7D
I
3
Input Bias Current
1
3
A
7D
Figure 5: Test and Evaluation Board Circuit
TYPICAL PERFORMANCES (using evaluation board) :
n = 83% (V
i
= 35V ; V
o
= V
REF
; I
o
= 5A ; f
SW
= 200KHz)
V
o RIPPLE
= 30mV (at 5A) with output filter capacitor ESR
60m
Line regulation = 5mV (V
i
= 15 to 50V)
Load regulation = 15mV (I
o
= 2 to 5A)
For component values, refer to test circuit part list.
L4975A
8/21
PARTS LIST
R
1
= 30K
C
1
, C
2
= 3300
F 63V
L
EYF (ROE
R
2
= 10K
C
3
, C
4
, C
5
, C
6
= 2.2
F
R
3
= 15K
C
7
= 390pF Film
R
4
= 16K
C
8
= 22nF MKT 1817 (ERO)
R
5
= 22
0,5W
R
6
= 4K7
C
9
= 2.2nF KP1830
R
7
= 10
C
10
= 220nF MKT
R
8
= see tab. A
C
11
= 2.2nF MP1830
R
9
= OPTION
**C
12
, C
13
, C
14
= 220
F 40V
L
EKR
R
10
= 4K7
C
15
= 1
F Film
R
11
= 10
D1 = MBR 760CT (or 7.5A/60V or equivalent)
L1 = 80
H
core 58930 MAGNETICS
24 TURNS 1.1mm (AWG 17)
COGEMA 949178
* 2 capacitors in parallel to increase input RMS current capability
** 3 capacitors in parallel to reduce total output ESR
Table B
SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency
Bootstrap Cap.c10
f = 20KHz
680nF
f = 50KHz
470nF
f = 100KHz
330nF
f = 200KHz
220nF
f = 500KHz
100nF
Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale).
Table A
V
0
R
9
R
7
12V
15V
18V
24V
4.7k
4.7k
4.7k
4.7k
6.2kW
9.1k
12k
18k
L4975A
9/21
Figure 7: DC Test Circuits
Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale)
L4975A
10/21
Figure 7A
Figure 7B
L4975A
11/21
Figure 7C
Figure 7D
L4975A
12/21
Figure 8: Quiescent Drain Current vs. Supply
Voltage (0% duty cycle - see fig. 7A).
Figure 10: Quiescent Drain Current vs. Duty
Cycle
Figure 12: Reference Voltage (pin 14) vs.
Junction Temperature (see fig. 7)
Figure 9: Quiescent Drain Current vs. Junction
Temperature (0% duty cycle).
Figure 11: Reference Voltage (pin14) vs. V
i
(see
fig. 7)
Figure 13: Reference Voltage (pin15) vs. V
i
(see
fig. 7)
L4975A
13/21
Figure 14: Reference Voltage (pin 15) vs.
Junction Temperature (see fig. 7)
Figure 16: Switching Frequency vs. Input
Voltage (see fig. 5)
Figure 18: Switching Frequency vs. R4 (see fig. 5)
Figure 15: Reference Voltage 5.1V (pin 14)
Supply Voltage Ripple Rejection vs.
Frequency
Figure 17: Switching Frequency vs. Junction
Temperature (see fig 5)
Figure 19: Max. Duty Cycle vs. Frequency
L4975A
14/21
Figure 20: Supply Voltage Ripple Rejection vs.
Frequency (see fig. 5)
Figure 22: Load Transient Response (see fig. 5)
Figure 24: Dropout Voltage Between Pin 9 and
Pin 7 vs. Junction Temperature
Figure 21: Line Transient Response (see fig. 5)
Figure 23: Dropout Voltage Between Pin 9 and
Pin 7 vs. Current at Pin 7
Figure 25: Power Dissipation (device only) vs.
Input Voltage
L4975A
15/21
Figure 26: Power Dissipation (device only) vs.
Output Voltage
Figure 28: Efficiency vs. Output Current
Figure 30: Efficiency vs. Output Voltage
Figure 27: Heatsink Used to Derive the Device's
Power Dissipation
R
th
- Heatsink =
T
case
-
T
amb
P
d
Figure 29: Efficiency vs. Output Voltage
Figure 31: Open Loop Frequency and Phase
Response of Error Amplifier (see
fig.7C)
L4975A
16/21
Figure 32: Power Dissipation Derating Curve
Figure 33: 5.1V/12V Multiple Supply. Note the Synchronization between the L4975A and the L4974A
L4975A
17/21
Figure 34: 5.1V / 5A Low Cost Application
Figure 35: 5A Switching Regulator, Adjustable from 0V to 25V.
L4975A
18/21
Figure 36: L4975A's Sync. Example
L4975A
19/21
Multiwatt15 V
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
5
0.197
B
2.65
0.104
C
1.6
0.063
D
1
0.039
E
0.49
0.55
0.019
0.022
F
0.66
0.75
0.026
0.030
G
1.02
1.27
1.52
0.040
0.050
0.060
G1
17.53
17.78
18.03
0.690
0.700
0.710
H1
19.6
0.772
H2
20.2
0.795
L
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.870
0.886
L2
17.65
18.1
0.695
0.713
L3
17.25
17.5
17.75
0.679
0.689
0.699
L4
10.3
10.7
10.9
0.406
0.421
0.429
L7
2.65
2.9
0.104
0.114
M
4.25
4.55
4.85
0.167
0.179
0.191
M1
4.63
5.08
5.53
0.182
0.200
0.218
S
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
OUTLINE AND
MECHANICAL DATA
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