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Электронный компонент: L5991

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L5991
L5991A
PRIMARY CONTROLLER WITH STANDBY
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT (< 120
A)
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100%AND 50% MAXIMUM DUTY CYCLE LIMIT
STANDBY FUNCTION
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention, and
Standby function for oscillator frequency reduction
when the converter is lightly loaded.
August 1999
+
-
+
-
TIMING
2
3
+
-
14
T
Vref
CLK
2.5V
+
-
1.2V
13
BLANKING
PWM
FAULT
SOFT-START
R
S
Q
25V
15V/10V
VREF OK
DIS
+
-
E/A
1V
R
2R
DIS
2.5V
7
6
5
11
10
9
4
8
15
1
13V
PWM UVLO
12
SGND
COMP
SS
ISEN
DIS
DC
RCT
SYNC
DC-LIM
V
CC
VREF
D97IN725A
VFB
PGND
OUT
V
C
OVER CURRENT
STAND-BY
ST-BY
VREF
16
BLOCK DIAGRAM
ORDERING NUMBERS: L5991/L5991A (DIP16)
L5991D/L5991AD (SO16)
MULTIPOWER BCD TECHNOLOGY
DIP16
SO16
1/23
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (I
CC
< 50mA) (*)
selflimit
V
I
OUT
Output Peak Pulse Current
1.5
A
Analog Inputs & Outputs (6,7)
-0.3 to 8
V
Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16)
-0.3 to 6
V
P
tot
Power Dissipation @ T
amb
= 70
C (DIP16)
@ T
amb
= 50
C (SO16)
1
0.83
W
W
T
j
Junction Temperature, Operating Range
-40 to 150
C
T
stg
Storage Temperature, Operating Range
-55 to 150
C
(*) maximum package power dissipation limits must be observed
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction -Ambient (DIP16)
80
C/W
Thermal Resistance Junction -Ambient (SO16)
120
C/W
PIN FUNCTIONS
N.
Name
Fun ction
1
SYNC
Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
2
RCT
Oscillator pin for external C
T
, R
A
, R
B
components
3
DC
Duty Cycle control
4
VREF
5.0V +/-1.5% reference voltage @ 25
C
5
VFB
Error Amplifier Inverting input
6
COMP
Error Amplifier Output
7
SS
Soft start pin for external capacitor Css
8
V
CC
Supply for internal "Signal" circuitry
9
V
C
Supply for Power section
10
OUT
High current totem pole output
11
PGND
Power ground
12
SGND
Signal ground
13
ISEN
Current sense
14
DIS
Disable. It must never be left floating. TIE to SGND if not used.
15
DC-LIM
Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is
imposed
16
ST-BY
Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.
SYNC
RCT
DC
VREF
VFB
SS
COMP
1
3
2
4
5
6
7
OUT
SGND
PGND
ISEN
DIS
DC-LIM
ST-BY
16
15
14
13
12
10
11
V
CC
8
V
C
9
PIN CONNECTION
L5991 - L5991A
2/23
ELECTRICAL CHARACTERISTICS (V
CC
= 15V; T
j
= 0 to 105
C; R
T
= 13.3k
(*) C
T
= 1nF;
unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
REFERENCE SECTION
V
REF
Output Voltage
T
j
= 25
C; I
O
= 1mA
4.925
5.0
5.075
V
Line Regulation
V
CC
= 12 to 20V; T
j
= 25
C
2.0
10
mV
Load Regulation
I
O
= 1 to 10mA; T
j
= 25
C
2.0
10
mV
T
S
Temperature Stability
0.4
mV/
C
Total Variation
Line, Load, Temperature
4.80
5.0
5.130
V
I
OS
Short Circuit Current
Vref = 0V
30
150
mA
Power Down/UVLO
V
CC
= 6V; I
sink
= 0.5mA
0.2
0.5
V
OSCILLATOR SECTION
Initial Accuracy
pin 15 = Vref;
T
j
= 25
C
V
comp
= 4.5V
95
100
105
kHz
pin 15 = Vref; V
CC
= 12 to 20V
V
comp
= 4.5V
93
100
107
kHz
pin 15 = Vref; V
CC
= 12 to 20V
V
comp
= 2V
46.5
50
53.5
kHz
Duty Cycle
pin 3 = 0,7V, pin 15 = V
REF
pin 3 = 0.7V, pin 15 = OPEN
0
0
%
%
pin 3 = 3.2V, pin 15 = V
REF
pin 3 = 3.2V, pin 15 = OPEN
47
93
%
%
Duty Cycle Accuracy
pin 3 = 2.79V, pin 15 = OPEN
75
80
85
%
Oscillator Ramp Peak
2.8
3.0
3.2
V
Oscillator Ramp Valley
0.75
0.9
1.05
V
ERROR AMPLIFIER SECTION
Input Bias Current
V
FB
to GND
0.2
3.0
A
V
I
Input Voltage
V
COMP
= V
FB
2.42
2.5
2.58
V
G
OPL
Open Loop Gain
V
COMP
= 2 to 4V
60
90
dB
SVR
Supply Voltage Rejection
V
CC
= 12 to 20V
85
dB
V
OL
Output Low Voltage
I
sink
= 2mA
1.1
V
V
OH
Output High Voltage
I
sou rce
= 0.5mA, V
FB
= 2.3V
5
6
V
I
O
Output Source Current
V
COMP
> 4V, V
FB
= 2.3V
0.5
1.3
2.5
mA
Output Sink Current
V
COMP
= 1.1V, V
FB
= 2.7V
2
6
mA
Unit Gain Bandwidth
1.7
4
MHz
S
R
Slew Rate
8
V/
s
PWM CURRENT SENSE SECTION
I
b
Input Bias Current
I
sen
= 0
3
15
A
I
S
Maximum Input Signal
V
COMP
= 5V
0.92
1.0
1.08
V
Delay to Output
70
100
ns
Gain
2.85
3
3.15
V/V
V
t
Fault Threshold Voltage
1.1
1.2
1.3
V
SOFT START SECTION
I
SSC
SS Charge Current
T
j
= 25
C
14
20
26
A
I
SSD
SS Discharge Current
VSS = 0.6V T
j
= 25
C
5
10
15
A
V
SSSAT
SS Saturation Voltage
DC = 0%
0.6
V
V
SSCLAMP
SS Clamp Voltage
7
V
LEADING EDGE BLANKING
Internal Masking Time
100
ns
OUTPUT SECTION
V
OL
Output Low Voltage
I
O
= 250mA
1.0
V
V
OH
Output High Voltage
I
O
= 20mA; V
CC
= 12V
10
10.5
V
I
O
= 200mA; V
CC
= 12V
9
10
V
V
OUT CLAMP
Output Clamp Voltage
I
O
= 5mA; V
CC
= 20V
13
V
Collector Leakage
V
CC
= 20V V
C
= 24V
2
20
A
(*) R
T
= R
A
//R
B
, R
A
= R
B
= 27k
, see Fig. 22.
L5991 - L5991A
3/23
6
8
2 0
3 0
V 1 4 = 0, P in 2 = ope n
T j = 2 5
C
0
4
8
1 2
1 6
2 0
2 4
0
0 .0 5
0 .1
0 .1 5
0 .2
4
V c c [V ]
Iq [m A ]
2 8
X
Y
Figure 1. L5991 - Quiescent current vs. input
voltage.
(X = 7.6V and Y= 8.4V for L5991A)
0
4
8
1 2
1 6
2 0
2 4
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
3 0 0
3 5 0
V cc [ V ]
I q [
A ]
V 1 4 = V r e f
T j = 2 5
C
X
Y
Figure 2. L5991 - Quiescent current vs. input
voltage (after disable).
(X = 7.6V and Y= 8.4V for L5991A)
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OUTPUT SECTION
Fall Time
C
O
= 1nF
C
O
= 2.5nF
20
35
60
ns
ns
Rise Time
C
O
= 1nF
C
O
= 2.5nF
50
70
100
ns
ns
UVLO Saturation
V
CC
= V
C
= 0 to V
CCON
I
sink
= 10mA
1.0
V
SUPPLY SECTION
V
CCON
Startup voltage
L5991
L5991A
14
7.8
15
8.4
16
9
V
V
V
CCOFF
Minimum Operating Voltage
L5991
L5991A
9
7
10
7.6
11
8.2
V
V
V
hys
UVLO Hysteresis
L5991
L5991A
4.5
0.5
5
0.8
V
V
I
S
Start Up Current
Before Turn-on at:
V
CC
= V
C
= V
CCON
-0.5V
40
75
120
A
I
op
Operating Current
C
T
= 1nF, R
T
= 13.3k
, C
O
=1nF
9
13
mA
I
q
Quiescent Current
(After turn on), CT = 1nF,
R
T
= 13.3k
, C
O
=0nF
7.0
10
mA
V
Z
Zener Voltage
I
8
= 20mA
21
25
30
V
STANDBY FUNCTION
V
REF
-V
ST-BY
I
ST-BY
= 2mA
45
mV
V
T1
Standby Threshold
V
comp
Falling
2.5
V
V
comp
Rising
4.0
V
SYNCHRONIZATION SECTION
Master Operation
V
1
Clock Amplitude
I
SOURCE
= 0.8mA
4
V
I
1
Clock Source Current
Vclock = 3.5V
3
7
mA
Slave Operation
V
1
Sync Pulse
Low Level
1
V
High Level
3.5
V
I
1
Sync Pulse Current
VSYNC = 3.5V
0.5
mA
OVER CURRENT PROTECTION
V
t
Fault Threshold Voltage
1.1
1.2
1.3
V
DISABLE SECTION
Shutdown threshold
2.4
2.5
2.6
V
I
SH
Shutdown Current
V
CC
= 15V
330
A
L5991 - L5991A
4/23
8
1 0
1 2
1 4
1 6
1 8
2 0
2 2
2 4
7 .0
7 .5
8 .0
8 .5
9 .0
V c c
[V ]
Iq [m A ]
V 1 4 = 0 , V 5 = V re f
R t = 4 .5 K o h m ,T j = 2 5
C
5 0 0 K h z
3 0 0 K h z
1 M h z
1 0 0 K h z
Figure 3. Quiescent current vs. input voltage.
0
5
10
15
20
25
4.9
4.95
5
5.05
5.1
Iref [mA]
Vref [V]
Vcc=15V
Tj = 25
C
Figure 6. Reference voltage vs. load current.
-50
-25
0
25
50
75
100
125
150
4.9
4.95
5
5.05
5.1
Tj (
C)
Vref [V])
Vcc = 15V
Iref = 1mA
Figure 7. Vref vs. junction temperature.
-50
-25
0
25
50
75
100
125
150
4.9
4.95
5
5.05
5.1
Tj (
C)
Vref [V]
Vcc = 15V
Iref= 20mA
Figure 8. Vref vs. junction temperature.
8
1 0
12
1 4
16
1 8
2 0
2 2
0
6
1 2
1 8
2 4
3 0
3 6
V cc [ V ]
I q [ m A ]
C o = 1 n F, T j = 2 5
C
D C = 0 %
1 M H z
5 0 0 K H z
3 00 K Hz
1 0 0K Hz
Figure 4. Quiescent current vs. input voltage
and switching frequency.
8
10
12
14
16
18
20
22
0
6
12
18
24
30
36
Vcc [V]
Iq [mA]
Co= 1nF, Tj = 25
C
DC = 100%
1MHz
500KHz
300KHz
100KHz
Figure 5. Quiescent current vs. input voltage
and switching frequency.
L5991 - L5991A
5/23
10
0
0.2
0.4
0.6
0.8
1
1.2
6
8
10
12
14
16
Isource [A]
Vsat = V
[V]
Vcc = Vc = 15V
Tj = 25
C
Figure 10. Output saturation.
0
0.2
0. 4
0.6
0. 8
1
1. 2
0
0. 5
1
1. 5
2
2. 5
Isink [A ]
10
V sat = V
[V]
V cc = V c = 15V
T j = 25
C
Figure 11. Output saturation.
1
10
100
1000
10000
0
40
80
120
fsw (Hz)
SVRR (dB)
Vcc=15V
Vp-p=1V
Figure 9. Vref SVRR vs. switching frequency.
0
200
400
600
800
1,000 1,200 1,400
0
10
20
30
40
50
Vpin10 [mV]
Ipin10 [mA]
Vcc < Vccon
before turn-on
Figure 12. UVLO Saturation
10
20
30
40
10
20
50
100
200
500
1000
2000
5000
Rt (kohm)
fsw (KHz)
100pF
220pF
470pF
1 nF
2.2nF
5 .6nF
Tj = 25
C
Vcc
= 15V, V15 =0V
Figure 13. Timingresistor vs.switchingfrequency.
-50
-25
0
25
50
75
100
125
150
280
290
300
310
320
Tj (
C)
fsw (KHz)
R t= 4.5Kohm, C t = 1nF
Vcc = 15V, V15=Vref
Figure 14. Switching frequency vs. tempera-
ture.
L5991 - L5991A
6/23
0.01
0.1
1
10
100
1000
10000 100000
0
50
100
150
20
40
60
80
100
120
140
f (KHz)
G [dB]
Phase
Figure 19. E/A frequency response.
-50
-25
0
25
50
75
100
125
150
28
30
32
34
36
38
40
42
Tj (
C)
Delay to output (ns)
PIN10 = OPEN
1V pulse
on PIN13
Figure18.Delayto output vs junctiontemperature.
-50
-25
0
25
50
75
100
125
150
280
290
300
310
320
Tj (
C)
fsw (KHz)
Rt= 4.5Kohm, Ct = 1nF
Vcc = 15V, V15= 0
Figure 15. Switching frequency vs. temperature.
2
4
6
8
10
300
600
900
1,200
1,500
Timing capacitor Ct [nF]
Dead time [ns]
Rt =4.5Kohm
V15 = 0V
V15 = Vref
Figure 16. Dead time vs Ct.
0
10
20
30
40
50
60
70
80
90 100
1
1.5
2
2.5
3
3.5
Duty Cycle [%]
DC Control Voltage Vpin3 [V]
Rt = 4.5Kohm,
Ct = 1nF
V15 = 0V
V15 = Vref
Figure 17. Maximum Duty Cycle vs Vpin3.
L5991 - L5991A
7/23
STANDBY FUNCTION
The standby function, optimized for flyback topol-
ogy, automatically detects a light load condition
for the converter and decreases the oscillator fre-
quency on that occurrence. The normal oscillation
frequency is automatically resumed when the out-
put load builds up and exceeds a defined thresh-
old.
This function allows to minimize power losses re-
lated to switching frequency, which represent the
majority of losses in a lightly loaded flyback, with-
out giving up the advantages of a higher switching
frequency at heavy load.
This is accomplished by monitoring the output of
the Error Amplifier (V
COMP
) that depends linearly
on the peak primary current, except for an offset.
If the the peak primary current decreases (as a re-
sult of a decrease of the power demanded by the
load) and V
COMP
falls below a fixed threshold
(V
T1
), the oscillator frequency will be set to a
lower value (f
SB
). When the peak primary current
increases and V
COMP
exceeds a second threshold
(V
T2
) the oscillator frequency is set to the normal
value (f
osc
). An appropriate hysteresis (V
T2
-V
T1
)
prevents undesired frequency change when
power is such that V
COMP
moves close to the
threshold. This operation is shown in fig. 20.
Both the normal and the standby frequency are
externally programmable. V
T1
and V
T2
are inter-
nally fixed but it is possible to adjust the thresh-
olds in terms of input power level.
APPLICATION INFORMATION
Detailed Pin Function Description
Pin 1.
SYNC (In/Out Synchronization). This func-
tion allows the IC's oscillator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 22 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600
A internal sink current gener-
ator. During the falling edge, that is when the
pulse is released, the 600
A pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 21, some practical examples of synchroniz-
ing the L5991 are given.
Since the device automatically diminishes its op-
erating frequency under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operation and not to standby.
Pin 2. RCT (Oscillator). Two resistors (R
A
and R
B
)
and one capacitor (C
T
), connected as shown in
fig. 22, allow to set separately the operating fre-
quency of the oscillator in normal operation (f
osc
)
and in standby mode (f
SB
).
C
T
is charged from Vref through R
A
and R
B
in nor-
mal operation (STANDBY = HIGH), through R
A
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is gen-
erated.
When the voltage on C
T
reaches 3V, the capaci-
tor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
1
2
3
4
VCOMP
Pin
f
os c
f
SB
Stand-by
Normal operation
V
T1
P
NO
P
SB
V
T2
Figure 20. Standby dynamic operation.
L5991
L5991
R
A
VREF
SYNC
SYNC
RCT
RCT
L4981A
(MASTER)
L5991
(SLAVE)
R
A
VREF
SYNC
RCT
R
OSC
C
OSC
C
T
L5991
(MASTER)
L4981A
(SLAVE)
SYNC
R
OSC
C
T
C
OSC
SYNC
(a)
(b)
(c)
R
A
D97IN728A
C
T
VREF
4
1
2
1
2
16
18
17
4
2
1
RCT
1
2
4
16
17
18
ST-BY
16
R
B
ST-BY
16
R
B
R
B
16
ST-BY
Figure 21. Synchronizing the L5991.
L5991 - L5991A
8/23
The oscillation frequency can be established with
the aid of the diagrams of fig. 13, where R
T
will be
intended as the parallel of R
A
and R
B
in normal
operation and R
T
= R
A
in standby, or considering
the following approximate relationships:
f
osc
1
C
T
(
0.693
(
R
A
// R
B
) +
K
T
(
1
)
,
which gives the normal operating frequency, and:
f
SB
1
C
T
(
0.693
R
A
+
K
T
)
(
2
)
,
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
R
A
//
R
B
=
R
A
R
B
R
A
+
R
B
,
while K
T
is defined as:
K
T
=
90 V
15
=
VREF
160
V
15
=
GND
/OPEN
(
3
)
,
and is related to the duration of the falling-edge of
the sawtooth:
T
d
30
10
-
9
+
K
T
C
T
(
4
)
.
T
d
is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extreme of the
duty cycle range, D
x
(see pin 15 for D
X
definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
from fig. 13 or resulting from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from f
osc
to f
SB
, the ratio f
osc
/ f
SB
must not exceed 5.5.
If during normal operation the IC is to be synchro-
nized to an external oscillator, R
A
, R
B
and C
T
should be selected for a f
osc
lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme D
x
(see pin 15).
If D
max
is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V
3
= 5 - 2
(2-Dmax)
(5)
D
max
is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 23),
thus in case the device is synchronized to an ex-
ternal frequency f
ext
(and therefore the oscillator
amplitude is reduced), (5) changes into:
V
3
=
5
-
4
exp
-
D
max
R
T
C
T
f
ext
(6)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. D
MAX
= D
X
), the pin has to be left float-
ing. An internal pull-up (see fig. 23) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
+
-
R2
R3
R1
CLAMP
D1
50
R
A
C
T
D
R
Q
600
A
D97IN729A
V
REF
RCT
SYNC
CLK
2
4
1
16
ST-BY
R
B
STANDBY
Figure 22. Oscillator and synchronization internal schematic.
L5991 - L5991A
9/23
during ESD tests), it can be connected to VREF
through a 4.7k
resistor.
Pin 4. VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V
1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1
F typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affecting thereference.
Before device turn-on, this pin has a sink current ca-
pability of 0.5mA.
Pin 5. VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
Pin 6. COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple of compensation techniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into ac-
count. In particular, this means that the open-loop
crossover frequency must not exceed f
SB
/4
f
SB
/5.
The voltage on pin 6 is monitored in order to re-
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7. SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-start time, is approximately:
T
ss
3
R
sense
I
Qpk
I
SSC
C
ss
(7)
where R
sense
is the current sense resistor (see pin
13) and I
Qpk
is the switch peak current (flowing
through R
sense
), which depends on the output
load. Usually, C
SS
is selected for a T
SS
in the or-
der of milliseconds.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 24, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling procedure, named 'hiccup' mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 25 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as 'hiccup" period, is approximately given by:
T
hic
4.5
1
I
SSC
+
1
I
SSD
C
ss
(
8
)
+
-
R2
R1
R
A
C
T
D97IN727A
V
REF
RCT
DC
TO PWM LOGIC
4
3
2
23K
28K
3
A
R
B
ST-BY
16
Figure 23. Duty cycle control.
V
OUT
T
ON
D.C.M.
C.C.M.
D
A
B
C
I
Qpk
T
ON(min)
1-2 I
Qpk
I
Qpk(max)
I
OUT
I
SHORT
I
OUT(max)
D97IN495
Figure 24. Regulation characteristic and re-
lated quantities.
L5991 - L5991A
10/23
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
"Hiccup" keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the
current
consumption
is
extremely
low
(<150
A). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses in
standby.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 26,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is R
g
+ R
g'
, at
turn-off is R
g
only.
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT's (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
7V
T
hic
time
SHORT
I
OUT
I
SEN
FAULT
SS
5V
0.5V
D98IN986
Figure 25. Hiccup mode operation.
OUT
Rg
DRIVE &
CONTROL
13V
V
C
V
CC
Rg'
PGND
Rg(ON)=Rg+Rg'
Rg(OFF)=Rg
D97IN726
L5991
9
10
11
8
Figure 26. Turn-on and turn-off speeds adjust-
ment.
L5991 - L5991A
11/23
in fig.27) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from V
CC
= 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating, V
REFOK
is pulled high (refer to fig.
27) and the circuit is disabled.
It is then possible to omit the "bleeder" resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 12. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the "hot" lead of the current sense
resistor R
sense
(being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (I
Q
). When this voltage is equal
to:
V
13pk
=
I
Qpk
R
sense
=
V
COMP
-
1.4
3
(
9
)
the conduction of the switch is terminated.
To increase the noise immunity, a "Leading Edge
Blanking" of about 100ns is internally realized as
shown in fig. 28. Because of that, the smoothing
RC filter between this pin and R
sense
could be re-
moved or, at least, considerably reduced.
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
29. It is also possible to realize an overvoltage
protection, as shown in the section " Application
Ideas".If used, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
D
x
R
T
R
T
+
230
(
10
)
if DC-LIM is grounded or left floating. Instead,
+
-
I
D97IN503
ISEN
0
3V
CLK
2V
+
-
+
-
1.2V
FROM E/A
OVERCURRENT
COMPARATOR
PWM
COMPARATOR
TO PWM
LOGIC
TO FAULT
LOGIC
13
Figure 28. Internal LEB.
10
12
SGND
OUT
V
REFOK
D97IN538
Figure 27. Pull-Down of the output in UVLO.
L5991 - L5991A
12/23
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately at:
D
x
R
T
2
R
T
+
260
(
11
)
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram) is activated.
Fig. 30 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor C
T
(in order to get
duty cycles as close to 50% as possible) so the
oscillator frequency - with the same timing compo-
nents will be slightly higher.
Pin 16. S-BY (Standby Function). The resistor R
B
,
along with R
A
, sets the operating frequency of the
oscillator in normal operation (f
osc
). In fact, as long
as the STANDBY signal is high, the pin is inter-
nally connected to the reference voltage VREF by
a N-channel FET (see fig. 31), so the timing ca-
pacitor C
T
is charged through R
A
and R
B
. When
the STANDBY signal goes low the N-channel FET
is turned off and the pin becomes floating. R
B
is
+
-
C
D97IN502
DIS
D
R
Q
DISABLE
UVLO
2.5V
14
DISABLE
SIGNAL
Figure 29. Disable (Latched).
V15=GND
V5=V13=GND
V15=VREF
V5=V13=GND
t
d
t
d
tc
tc
V2
V10
V2
V10
D
X
=
tc
tc + td
D
X
=
tc
2 tc + td
D97IN498
Figure 30. Half duty cycle option.
-
+
-
+
2.5
2.5/4
R
STANDBY
10V
LEVEL SHIFT
COMP
FB
VREF
ST-BY
4
16
6
RCT
C
T
R
A
R
B
2
5
LOW
HIGH
STANDBY
D97IN752B
V
T1
2.5V
V
T2
4V
V
COMP
-
+
ISEN
13
R
DRIVER
OUT
STANDBY BLOCK
2R
Figure 31. Standby function internal schematic and operation.
L5991 - L5991A
13/23
now disconnected and C
T
is charged through R
A
only. In this way the oscillator frequency (f
SB
) will
be lower. Refer to pin 2 description to see how to
calculate the timing components.
Typical values for V
T1
and V
T2
are 2.5 V and 4V
respectively. This 1.5V hysteresis is enough to
prevent undesired frequency change up to a 5.5
to 1 f
osc
/ f
SB
ratio.
The value of V
T1
is such that in a discontinuous
flyback the standby frequency is activated when
the input power is about 13% of the maximum. If
necessary, it is possible to decrease the power
threshold below 13% by adding a DC offset (V
o
)
on the current sense pin (13, ISEN). This will also
allow a frequency change greater than 5.5 to 1.
The following equations,useful for design, apply:
P
inSB
=
1
2
L
P
osc
0.367
-
V
o
R
sense
2
(
12
)
,
P
inNO
=
1
2
L
P
SB
0.867
-
V
o
R
sense
2
(
13
)
,
osc
SB
<
0.867
-
V
o
0.367
-
V
o
2
(
14
)
,
where P
inSB
is the input power below which the
L5991 recognizes a light load and switches the
oscillator frequency from
osc
to f
SB
, P
inNO
is the
input power above which the L5991 switches
back from
SB
to
osc
and L
p
the primary induc-
tance of the flyback transformer.
Connect to Vref or leave open this pin when
stand-by function is not used.
Layout hints
Generally speaking a proper circuitboard layout is
vital for correct operation but is not an easy task.
Careful component placing, correct traces routing,
appropriate traces widths and, in case of high
voltages, compliance with isolation distances are
the major issues. The L5991 eases this task by
putting two pins at disposal for separate current
returns of bias (SGND) and switch drive currents
(PGND) The matter is complex and only few im-
portant points will be here reminded.
1) All current returns (signal ground, power
ground, shielding, etc.) should be routed sepa-
rately and should be connected only at a single
ground point.
2) Noise coupling can be reduced by minimizing
the area circumscribed by current loops. This
applies particularly to loops where high pulsed
currents flow.
3) For high current paths, the traces should be
doubled on the other side of the PCB whenever
possible: this will reduce both the resistance
and the inductance of the wiring.
4) Magnetic field radiation (and stray inductance)
can be reduced by keeping all traces carrying
switched currents as short as possible.
5) In general, traces carrying signal currents
should run far from traces carrying pulsed cur-
rents or with quickly swinging voltages. From
this viewpoint, particular care should be taken
of the high impedance points (current sense in-
put, feedback input, ...). It could be a good idea
to route signal traces on one PCB side and
power traces on the other side.
6) Provide adequate filtering of some crucial
points of the circuit, such as voltage references,
IC's supply pins, etc.
L5991 - L5991A
14/23
APPLICATION IDEAS
Here follows a series of ideas/suggestions aimed at
either improving performance or solving common
application problems of L5991 based supplies.
C02
0.1
F
C01
0.1
F
F01
AC
250V
T3.15A
88
to
270
VAC
BD01
R01
3.3
C03
220
F
400V
R18
47K
3W
C10
10nF
100V
LF01
R03
47K
10
R08
22
13
R11
1K
12
C05
100pF
11
R10
0.22
C04
47
F
8
9
14
16
R06
27
R12
330K
R13
47K
R9
24K
2
4
16
C07
1
F
R5
12K
6800pF
1
3
8
7
D06
1N4148
5
7
C09
8.2nF
R21
100
C08
3.3nF
6
Q01
STP6
NA60FI
4N35
18
15
13
14
16
17
C56
470
F
25V
C57
470
F
25V
11
12
10
D04
1N4148
R07
47
D05
1N4937
C52
100
F
250V
C54
220
F
100V
R52
47
C58
47
F
25V
D55
BYW100-100
D56
BYW100-100
R53
4.7K
R54
1K
C61
0.056
F
R58
4.7K
Q51
TL431
VR51
100K
R55
300K
R56
4.3K
C59
0.01
F
180V
65W
80V
10W
GND
6.3V
5W
+15V
5W
-15V
5W
D97IN730A
C62
100
F
100V
C55
1000
F
16V
D54
BYW100-100
D53
BYT11-600
D52
BYT13-800
C11
4700pF
4KV
C12
R19
4.7M
R20
4.7M
L5991
R04
47K
R16
750K
R17
750K
C06
C11
2.2nF
VAC(V)
Pin(W)
Pout(W)
88
2.95
110
3.10
220
3.90
270
4.40
2
Figure 32. Typical application circuit for computer monitors (90W).
L5991 - L5991A
15/23
4700pF
4KV
4700pF
4KV
4.7M
STP4NA60
4N35
220
2
x
330
F
35V
1K
0.022
F
2.7K
3.9K
28V
/
0.7A
GND
470
F
16V
BYW100-50
BYW98-100
BYW100-200
4.7M
12V
/
1.5A
5V
/
0.5A
C02
0.1
F
C01
0.1
F
F01
AC
250V
T1A
85
TO
265
Vac
BD01
2.2
LF01
10K
1.1M
BC337
10
22
13
1K
12
470pF
11
0.47
1/2
W
33
F/25V
8
9
14
15
22
33K
4.7K
47K
2
3
4
1
100nF
22K
3.3nF
16
7
330nF
470
470pF
6
BAT46
TL431
L5991
22V
1.1M
STK2N50
1N4937
5
5.6K
N1
N2
N3
N4
Naux
5.6K
5.6K
2
x
470
F
16V
5.1K
270K
100
F
400V
BZW06-154
D97IN618
VAC(V)
Pin(W)
Pout(W)
85
0.90
110
0.93
220
1.14
265
1.57
0.55
Figure 33. Typical application circuit for inkjet printers (40W).
L5991 - L5991A
16/23
L5991
12
4
13
SGND
VREF
ISEN
OPTIONAL
D97IN751A
10
R
SENSE
R
A
R
Figure 34. Standby thresholds adjustment.
D97IN761
L5991
PGND
ISEN
OUT
V
C
SGND
V
IN
ISOLATION
BOUNDARY
10
9
13
11
12
Figure 35. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.
L5991
V
REF
T
V
CC
V
IN
20V
D97IN762B
2.2M
33K
SELF-SUPPLY
WINDING
8
4
12
11
47K
STD1NB50-1
Figure 36. Low consumption start-up.
D97IN763
L5991
PGND
ISEN
OUT
V
C
V
IN
9
10
13
11
8
V
CC
Figure 37. Bipolar transistor driver.
L5991 - L5991A
17/23
D97IN507
+
-
EA
R
i
+
1.3mA
R
d
R
2R
12
C
f
R
f
6
5
From V
O
2.5V
+
-
EA
R
P
+
1.3mA
R
d
R
2R
12
C
f
R
f
6
5
From V
O
2.5V
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
C
P
R
i
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
VFB
VFB
COMP
COMP
SGND
SGND
Figure 38. Typical E/A compensation networks.
L5991
COMP
D97IN759
TL431
V
OUT
VFB
6
5
Figure 39. Feedback with optocoupler.
L5991
OPTIONAL
D97IN760A
I
V
REF
SGND
R
A
C
T
RCT
R
SLOPE
R
SENSE
ISEN
L5991
OPTIONAL
I
V
REF
SGND
R
A
C
T
RCT
R
SLOPE
R
SENSE
ISEN
L5991
OPTIONAL
OUT
SGND
R
R
SLOPE
R
SENSE
ISEN
C
SLOPE
4
2
13
12
4
2
13
12
13
12
10
R
B
16
ST-BY
16
ST-BY
R
B
Figure 40. Slope compensation techniques.
L5991 - L5991A
18/23
Figure 41. Protection against overvoltage/feedback disconnection (latched)
L5991
D97IN755A
DC
V
CC
VREF
R
START
3
12
8
4
11
Figure 42 Protection against overvoltage/feed-
back disconnection (not latched)
D97IN756A
PGND
L5991
OPTIONAL
VREF
SGND
DIS
ISEN
I
4
14
13
12
11
R
SENSE
R
2
R
1
I
pk
I
pk max
2.5
R
SENSE
1-
R
2
R
1
Figure 43. Device shutdown on overcurrent
D97IN757
PGND
L5991
OUT
SGND
ISEN
Lp
R
FF
R
V
IN
R
FF
= 610
6
RLp
RSENSE
RSENSE
13
10
12
11
80
400V
DC
Figure 44. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
L5991
DC
10K
COMP
3
6
12
13
SGND
ISEN
D97IN758A
Figure 45. Voltage mode operation.
L5991
D98IN905
SGND
DIS
V
CC
R
START
PGND
8
14
12
11
V
Z
2.2K
L5991
D97IN754
SGND
DIS
V
CC
R
START
PGND
8
14
12
11
L5991 - L5991A
19/23