1/25
L6235
September 2003
s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
s
5.6A OUTPUT PEAK CURRENT (2.8A DC)
s
R
DS(ON)
0.3
TYP. VALUE @ T
j
= 25 C
s
OPERATING FREQUENCY UP TO 100KHz
s
NON DISSIPATIVE OVERCURRENT
DETECTION AND PROTECTION
s
DIAGNOSTIC OUTPUT
s
CONSTANT t
OFF
PWM CURRENT CONTROLLER
s
SLOW DECAY SYNCHR. RECTIFICATION
s
60 & 120 HALL EFFECT DECODING LOGIC
s
BRAKE FUNCTION
s
TACHO OUTPUT FOR SPEED LOOP
s
CROSS CONDUCTION PROTECTION
s
THERMAL SHUTDOWN
s
UNDERVOLTAGE LOCKOUT
s
INTEGRATED FAST FREEWEELING DIODES
DESCRIPTION
The L6235 is a DMOS Fully Integrated Three-Phase
Motor Driver with Overcurrent Protection.
Realized in MultiPower-BCD technology, the device
combines isolated DMOS Power Transistors with
CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to drive a
three-phase BLDC motor including: a three-phase
DMOS Bridge, a constant off time PWM Current Con-
troller and the decoding logic for single ended hall
sensors that generates the required sequence for the
power stage.
Available in PowerDIP24 (20+2+2), PowerSO36 and
SO24 (20+2+2) packages, the L6235 features a non-
dissipative overcurrent protection on the high side
Power MOSFETs and thermal shutdown.
BLOCK DIAGRAM
CHARGE
PUMP
VOLTAGE
REGULATOR
HALL-EFFECT
SENSORS
DECODING
LOGIC
THERMAL
PROTECTION
TACHO
MONOSTABLE
OCD1
OCD
OCD
OCD2
10V
5V
VCP
VS
A
GATE
LOGIC
VBOOT
V
BOOT
OUT1
OUT2
SENSE
A
VS
B
OUT3
SENSE
B
DIAG
EN
FWD/REV
BRAKE
H
3
H
1
RCPULSE
D99IN1095B
TACHO
RCOFF
H
2
OCD3
ONE SHOT
MONOSTABLE
MASKING
TIME
V
BOOT
OCD1
10V
V
BOOT
OCD2
10V
V
BOOT
OCD3
10V
SENSE
COMPARATOR
+
-
PWM
VREF
ORDERING NUMBERS:
L6235N
L6235PD
L6235D
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
DMOS DRIVER FOR
THREE-PHASE BRUSHLESS DC MOTOR
L6235
2/25
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITION
Symbol
Parameter
Test conditions
Value
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
60
V
V
OD
Differential Voltage between:
VS
A
, OUT
1
, OUT
2
, SENSE
A
and VS
B
, OUT
3
, SENSE
B
V
SA
= V
SB
= V
S
= 60V;
V
SENSEA
= V
SENSEB
= GND
60
V
V
BOOT
Bootstrap Peak Voltage
V
SA
= V
SB
= V
S
V
S
+ 10
V
V
IN
, V
EN
Logic Inputs Voltage Range
-0.3 to 7
V
V
REF
Voltage Range at pin VREF
-0.3 to 7
V
V
RCOFF
Voltage Range at pin RCOFF
-0.3 to 7
V
V
RCPULSE
Voltage Range at pin RCPULSE
-0.3 to 7
V
V
SENSE
Voltage Range at pins SENSE
A
and SENSE
B
-1 to 4
V
I
S(peak)
Pulsed Supply Current (for each
VS
A
and VS
B
pin)
V
SA
= V
SB
= V
S
; T
PULSE
< 1ms
7.1
A
I
S
DC Supply Current (for each
VS
A
and VS
B
pin)
V
SA
= V
SB
= V
S
2.8
A
T
stg
, T
OP
Storage and Operating
Temperature Range
-40 to 150
C
Symbol
Parameter
Test Conditions
MIN
MAX
Unit
V
S
Supply Voltage
V
SA
= V
SB
= V
S
12
52
V
V
OD
Differential Voltage between:
VS
A
, OUT
1
, OUT
2
, SENSE
A
and
VS
B
, OUT
3
, SENSE
B
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
52
V
V
REF
Voltage Range at pin VREF
-0.1
5
V
V
SENSE
Voltage Range at pins SENSE
A
and SENSE
B
(pulsed t
W
< t
rr
)
(DC)
-6
-1
6
1
V
V
I
OUT
DC Output Current
V
SA
= V
SB
= V
S
2.8
A
T
J
Operating Junction Temperature
-25
125
C
f
SW
Switching Frequency
100
KHz
3/25
L6235
THERMAL DATA
PIN CONNECTIONS (Top view)
(5) The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Symbol
Description
PDIP24
SO24
PowerSO36
Unit
R
th(j-pins)
Maximum Thermal Resistance Junction-Pins
18
14
C/W
R
th(j-case)
Maximum Thermal Resistance Junction-Case
1
C/W
R
th(j-amb)1
MaximumThermal Resistance Junction-Ambient
(1)
(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm
2
(with a thickness of 35 m).
43
51
-
C/W
R
th(j-amb)1
Maximum Thermal Resistance Junction-Ambient
(2)
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 m).
-
-
35
C/W
R
th(j-amb)1
MaximumThermal Resistance Junction-Ambient
(3)
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 m),
16 via holes and a ground layer.
-
-
15
C/W
R
th(j-amb)2
Maximum Thermal Resistance Junction-Ambient
(4)
(4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.
58
77
62
C/W
GND
GND
TACHO
RCPULSE
SENSE
B
EN
FWD/REV
1
3
2
4
5
6
7
8
9
VREF
VBOOT
BRAKE
OUT3
VS
B
GND
GND
19
18
17
16
15
13
14
D01IN1194A
10
11
12
24
23
22
21
20
H1
DIAG
SENSE
A
RCOFF
OUT1
VS
A
OUT2
VCP
H2
H3
GND
N.C.
N.C.
VS
A
RCOFF
OUT1
N.C.
N.C.
N.C.
N.C.
N.C.
TACHO
RCPULSE
N.C.
VS
B
N.C.
N.C.
GND
1
3
2
4
13
14
15
16
17
34
33
24
23
22
20
21
19
35
18
36
GND
GND
D01IN1195A
H1
SENSE
A
DIAG
SENSE
B
EN
FWD/REV
10
11
12
27
26
25
H3
VREF
9
28
OUT2
H2
VCP
BRAKE
OUT3
VBOOT
5
7
8
32
30
29
N.C.
N.C.
6
31
PowerSO36
(5)
PowerDIP24/SO24
L6235
4/25
PIN DESCRIPTION
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
1
10
H
1
Sensor Input
Single Ended Hall Effect Sensor Input 1.
2
11
DIAG
Open Drain
Output
Overcurrent Detection and Thermal Protection pin. An
internal open drain transistor pulls to GND when an
overcurrent on one of the High Side MOSFETs is
detected or during Thermal Protection.
3
12
SENSE
A
Power Supply
Half Bridge 1 and Half Bridge 2 Source Pin. This pin
must be connected together with pin SENSE
B
to
Power Ground through a sensing power resistor.
4
13
RCOFF
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current
Controller OFF-Time.
5
15
OUT
1
Power Output
Output 1
6, 7,
18, 19
1, 18,
19, 36
GND
GND
Ground terminals. On PowerDIP24 and SO24
packages, these pins are also used for heat
dissipation toward the PCB. On PowerSO36 package
the slug is connected on these pins.
8
22
TACHO
Open Drain
Output
Frequency-to-Voltage open drain output. Every pulse
from pin H
1
is shaped as a fixed and adjustable length
pulse.
9
24
RCPULSE
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the duration of the
Monostable Pulse used for the Frequency-to-Voltage
converter.
10
25
SENSE
B
Power Supply
Half Bridge 3 Source Pin. This pin must be connected
together with pin SENSE
A
to Power Ground through a
sensing power resistor. At this pin also the Inverting
Input of the Sense Comparator is connected.
11
26
FWD/REV
Logic Input
Selects the direction of the rotation. HIGH logic level
sets Forward Operation, whereas LOW logic level sets
Reverse Operation.
If not used, it has to be connected to GND or +5V..
12
27
EN
Logic Input
Chip Enable. LOW logic level switches OFF all Power
MOSFETs.
If not used, it has to be connected to +5V.
13
28
VREF
Logic Input
Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
14
29
BRAKE
Logic Input
Brake Input pin. LOW logic level switches ON all High
Side Power MOSFETs, implementing the Brake
Function.
If not used, it has to be connected to +5V.
15
30
VBOOT
Supply Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs.
16
32
OUT
3
Power Output
Output 3.
17
33
VS
B
Power Supply
Half Bridge 3 Power Supply Voltage. It must be
connected to the supply voltage together with pin VS
A
.
5/25
L6235
PACKAGE
Name
Type
Function
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
20
4
VS
A
Power Supply
Half Bridge 1 and Half Bridge 2 Power Supply Voltage.
It must be connected to the supply voltage together
with pin VS
B
.
21
5
OUT
2
Power Output
Output 2.
22
7
VCP
Output
Charge Pump Oscillator Output.
23
8
H
2
Sensor Input
Single Ended Hall Effect Sensor Input 2.
24
9
H
3
Sensor Input
Single Ended Hall Effect Sensor Input 3.
ELECTRICAL CHARACTERISTICS
(V
S
= 48V , T
amb
= 25 C , unless otherwise specified)
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
V
Sth(ON)
Turn ON threshold
6.6
7
7.4
V
V
Sth(OFF)
Turn OFF threshold
5.6
6
6.4
V
I
S
Quiescent Supply Current
All Bridges OFF;
Tj = -25 to 125C
(6)
5
10
mA
T
J(OFF)
Thermal Shutdown Temperature
165
C
Output DMOS Transistors
R
DS(ON)
High-Side Switch ON Resistance
T
j
= 25
C
0.34
0.4
T
j
=125
C
(6)
0.53
0.59
Low-Side Switch ON Resistance
T
j
= 25
C
0.28
0.34
T
j
=125
C
(6)
0.47
0.53
I
DSS
Leakage Current
EN = Low; OUT = V
CC
2
mA
EN = Low; OUT = GND
-0.15
mA
Source Drain Diodes
V
SD
Forward ON Voltage
I
SD
= 2.8A, EN = LOW
1.15
1.3
V
t
rr
Reverse Recovery Time
I
f
= 2.8A
300
ns
t
fr
Forward Recovery Time
200
ns
Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE)
V
IL
Low level logic input voltage
-0.3
0.8
V
V
IH
High level logic input voltage
2
7
V
I
IL
Low level logic input current
GND Logic Input Voltage
-10
A
I
IH
High level logic input current
7V Logic Input Voltage
10
A
V
th(ON)
Turn-ON Input Threshold
1.8
2.0
V
V
th(OFF)
Turn-OFF Input Threshold
0.8
1.3
V
V
thHYS
Input Thresholds Hysteresys
0.25
0.5
V
PIN DESCRIPTION (continued)
L6235
6/25
(6) Tested at 25C in a restricted range and guaranteed by characterization.
(7) See Fig. 1.
(8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(9) See Fig. 2.
Symbol
Parameter Test
Conditions
Min
Typ
Max
Unit
Switching Characteristics
t
D(on)EN
Enable to out turn-ON delay time
(7)
I
LOAD
= 2.8 A, Resistive Load
110
250
400
ns
t
D(off)EN
Enable to out turn-OFF delay time
(7)
I
LOAD
= 2.8 A, Resistive Load
300
550
800
ns
t
D(on)IN
Other Logic Inputs to Output Turn-
ON delay Time
I
LOAD
= 2.8 A, Resistive Load
2
s
t
D(off)IN
Other Logic Inputs to out Turn-OFF
delay Time
I
LOAD
= 2.8 A, Resistive Load
2
s
t
RISE
Output Rise Time
(7)
I
LOAD
= 2.8 A, Resistive Load
40
250
ns
t
FALL
Output Fall Time
(7)
I
LOAD
= 2.8 A, Resistive Load
40
250
ns
t
DT
Dead Time
0.5
1
s
f
CP
Charge Pump Frequency
Tj = -25 to 125C
(6)
0.6
1
MHz
PWM Comparator and Monostable
I
RCOFF
Source current at pin RC
OFF
V
RCOFF
= 2.5 V
3.5
5.5
mA
V
OFFSET
Offset Voltage on Sense
Comparator
V
ref
= 0.5 V
5
mV
t
prop
Turn OFF Propagation delay
(8)
V
ref
= 0.5 V
500
ns
t
blank
Internal Blanking Time on Sense
Comparator
1
s
t
ON(min)
Minimum on Time
1.5
2
s
t
OFF
PWM RecirculationTime
R
OFF
= 20k
; C
OFF
=
1nF
13
s
R
OFF
= 100k
; C
OFF
=
1nF
61
s
I
BIAS
Input Bias Current at pin VREF
10
A
Tacho Monostable
I
RCPULSE
Source Current at pin RCPULSE
V
RCPULSE
= 2.5V
3.5
5.5
mA
t
PULSE
Monostable of Time
R
PUL
= 20k
; C
PUL
=
1nF
12
s
R
PUL
= 100k
; C
PUL
=
1nF
60
s
R
TACHO
Open Drain ON Resistance
40
60
Over Current Detection & Protection
I
SOVER
Supply Overcurrent Protection
Threshold
T
J
= -25 to 125C
(6)
4.0
5.6
7.1
A
R
OPDR
Open Drain ON Resistance
I
DIAG
= 4mA
40
60
I
OH
OCD high level leakage current
V
DIAG
= 5V
1
A
t
OCD(ON)
OCD Turn-ON Delay Time
(9)
I
DIAG
= 4mA; C
DIAG
< 100pF
200
ns
t
OCD(OFF)
OCD Turn-OFF Delay Time
(9)
I
DIAG
= 4mA; C
DIAG
< 100pF
100
ns
ELECTRICAL CHARACTERISTICS (continued)
(V
S
= 48V , T
amb
= 25 C , unless otherwise specified)
7/25
L6235
Figure 1. Switching Characteristic Definition
Figure 2. Overcurrent Detection Timing Definition
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
I
SOVER
90%
10%
I
OUT
V
DIAG
t
OCD(OFF)
t
OCD(ON)
D02IN1387
ON
OFF
BRIDGE
L6235
8/25
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6235 integrates a Three-Phase Bridge, which
consists of 6 Power MOSFETs connected as shown
on the Block Diagram. Each Power MOS has an
R
DS(ON)
= 0.3
(typical value @25C) with intrinsic
fast freewheeling diode. Switching patterns are gen-
erated by the PWM Current Controller and the Hall
Effect Sensor Decoding Logic (see relative para-
graphs). Cross conduction protection is implemented
by using a dead time (t
DT
= 1s typical value) set by
internal timing circuit between the turn off and turn on
of two Power MOSFETs in one leg of a bridge.
Pins VS
A
and VS
B
MUST be connected together to
the supply voltage (V
S
).
Using N-Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped Supply
(V
BOOT
) is obtained through an internal oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output (pin
VCP) is a square wave at 600KHz (typically) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Component
Values.
Figure 3. Charge Pump Circuit
LOGIC INPUTS
Pins FWD/REV, BRAKE, EN, H
1
, H
2
and H
3
are TTL/
CMOS and C compatible logic inputs. The internal
structure is shown in Figure 4. Typical value for turn-
ON and turn-OFF thresholds are respectively V
th(ON)
= 1.8V and V
th(OFF)
= 1.3V.
Pin EN (enable) may be used to implement Overcurrent
and Thermal protection by connecting it to the open col-
lector DIAG output If the protection and an external dis-
able function are both desired, the appropriate
connection must be implemented. When the external
signal is from an open collector output, the circuit in Fig-
ure 5 can be used . For external circuits that are push
pull outputs the circuit in Figure 6 could be used. The re-
sistor R
EN
should be chosen in the range from 2.2K
to
180K
. Recommended values for R
EN
and C
EN
are re-
spectively 100K
and 5.6nF. More information for se-
lecting the values can be found in the Overcurrent
Protection section.
Figure 4. Logic Input Internal Structure
Figure 5. Pin EN Open Collector Driving
Figure 6. Pin EN Push-Pull Driving
C
BOOT
220nF
C
P
10nF
R
P
100
D
1
1N4148
D
2
1N4148
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP
VBOOT
VS
B
D01IN1328
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
DIAG
D02IN1378
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
D02IN1379
DIAG
ESD
PROTECTION
9/25
L6235
PWM CURRENT CONTROL
The L6235 includes a constant off time PWM Current Controller. The current control circuit senses the bridge
current by sensing the voltage drop across an external sense resistor connected between the source of the
three lower power MOS transistors and ground, as shown in Figure 7. As the current in the motor increases the
voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor be-
comes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable
switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current
recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section. When the
monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent cross conduc-
tion in the bridge, delays the turn on of the power MOS, the effective Off Time t
OFF
is the sum of the monostable
time plus the dead time.
Figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-
verse recovery of the freewheeling diodes. The L6235 provides a 1s Blanking Time t
BLANK
that inhibits the
comparator output so that the current spike cannot prematurely retrigger the monostable.
Figure 7. PWM Current Controller Simplified Schematic
DRIVERS
+
DEAD TIME
S
Q
R
DRIVERS
+
DEAD TIME
DRIVERS
+
DEAD TIME
OUT3
OUT2
SENSEB
SENSEA
RSENSE
D02IN1380
RCOFF
R
OFF
C
OFF
VREF
OUT1
+
+
-
-
1
s
5mA
BLANKER
SENSE
COMPARATOR
MONOSTABLE
SET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
BLANKING TIME
MONOSTABLE
VS
B
VS
VS
A
TO GATE
LOGIC
(0)
(1)
L6235
10/25
Figure 8. Output Current Regulation Waveforms
Figure 9 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately cal-
culated from the equations:
t
RCFALL
= 0.6 R
OFF
C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 R
OFF
C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
R
OFF
100K
0.47nF
C
OFF
100nF
t
DT
= 1s (typical value)
Therefore:
t
OFF(MIN)
= 6.6s
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Rise Time t
RCRISE
of the voltage at the pin RCOFF. The
Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the On Time t
ON
, which depends by motors and supply parameters, has to
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the On Time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
t
RCRISE
= 600 C
OFF
OFF
B
C
D
D
A
t
ON
t
OFF
B
C
ON
2.5V
0
Slow Decay
Slow Decay
1
s t
BLANK
t
RCRISE
t
RCRISE
SYNCHRONOUS RECTIFICATION
1
s t
BLANK
5V
V
RC
V
SENSE
V
REF
I
OUT
V
REF
R
SENSE
D02IN1351
t
OFF
1
s t
DT
1
s t
DT
t
RCFALL
t
RCFALL
t
ON
t
ON MI N
(
)
>
1.5
s (typ. value)
=
t
O N
t
RCRISE
t
DT
>
11/25
L6235
Figure 10 shows the lower limit for the On Time t
ON
for having a good PWM current regulation capacity. It has
to be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be smaller
than t
RCRISE
- t
DT
. In this last case the device continues to work but the Off Time t
OFF
is not more constant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller On Time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the circuit
performance.
Figure 9. t
OFF
versus C
OFF
and R
OFF
.
Figure 10. Area where t
ON
can vary maintaining the PWM regulation.
0.1
1
10
100
1
10
100
1.10
3
1.10
4
Coff [nF]
to
ff [
s]
R
off
= 100k
R
off
= 47k
R
off
= 20k
0.1
1
10
100
1
10
100
Coff [nF]
to
n
(
m
i
n
)
[
s]
1.5
s (typ. value)
L6235
12/25
SLOW DECAY MODE
Figure 11 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two
legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure
and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current
recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slow-
ly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the
impendence of the freewheeling diode and the related conducting losses. When the monostable times out, up-
per MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after
some delay set by the Dead Time to prevent cross conduction.
Figure 11. Slow Decay Mode Output Stage Configurations
DECODING LOGIC
The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase
bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3-
phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors
spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a uni-
versal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor posi-
tions with 120 electrical degrees sensor phasing (see Figure 12, positions 1, 2, 3a, 4, 5 and 6a) and six combi-
nations are valid for rotor positions with 60 electrical degrees phasing (see Figure 14, positions 1, 2, 3b, 4, 5
and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec-
trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas-
ing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the Table 2. For any input
configuration (H
1
, H
2
and H
3
) there is one output configuration (OUT
1
, OUT
2
and OUT
3
). The output configura-
tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the
Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive
the motor with all the four conventions by changing the direction set.
A) ON TIME
B) 1
s DEAD TIME
C) SYNCHRONOUS
RECTIFICATION
D) 1
s DEAD TIME
D01IN1336
13/25
L6235
Table 2. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.
Figure 12. 120 Hall Sensor Sequence.
Figure 13. 60 Hall Sensor Sequence.
Hall 120
1
2
3a
-
4
5
6a
-
Hall 60
1
2
-
3b
4
5
-
6b
H
1
H
H
L
H
L
L
H
L
H
2
L
H
H
H
H
L
L
L
H
3
L
L
L
H
H
H
H
L
OUT
1
Vs
High Z
GND
GND
GND
High Z
Vs
Vs
OUT
2
High Z
Vs
Vs
Vs
High Z
GND
GND
GND
OUT
3
GND
GND
High Z
High Z
Vs
Vs
High Z
High Z
Phasing
1->3
2->3
2->1
2->1
3->1
3->2
1->2
1->2
H
1
H
2
H
2
H
2
H
2
H
2
H
3
H
3
H
3
H
3
H
3
H
1
H
1
H
1
H
1
H
3
H
2
H
1
1
2
3a
4
5
6a
= H
= L
H
1
H
1
H
2
H
2
H
2
H
2
H
2
H
3
H
3
H
3
H
3
H
3
H
1
H
1
H
1
H
1
H
3
H
2
1
2
3b
4
5
6b
= H
= L
L6235
14/25
TACHO
A tachometer function consists of a monostable, with constant off time (t
PULSE
), whose input is one Hall Effect
signal (H
1
). It allows developing an easy speed control loop by using an external op amp, as shown in Figure
14. For component values refer to Application Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors
H
1
, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time
t
PULSE
(see Figure 15). The off time t
PULSE
can be set using the external RC network (R
PUL
, C
PUL
) connected
to the pin RCPULSE. Figure 16 gives the relation between t
PULSE
and C
PUL
, R
PUL
. We have approximately:
t
PULSE
= 0.6 R
PUL
C
PUL
where C
PUL
should be chosen in the range 1nF ... 100nF and R
PUL
in the range 20K
... 100K
.
By connecting the tachometer pin to an external pull-up resistor, the output signal average value V
M
is propor-
tional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Fre-
quency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a
reference voltage V
REF
, which sets the speed of the motor.
Figure 14. Tacho Operation Waveforms.
V
M
t
P ULS E
T
------------------
V
DD
=
T
t
PULSE
H
1
V
TACHO
H
2
H
3
V
M
V
DD
15/25
L6235
Figure 15. Tachometer Speed Control Loop.
Figure 16. t
PULSE
versus C
PUL
and R
PUL
.
C
REF2
R
PUL
C
PUL
R
DD
R
3
R
2
R
1
C
1
C
REF1
VREF
TACHO
H
1
TACHO
MONOSTABLE
RCPULSE
V
DD
V
REF
R
4
1
10
100
10
100
1 .10
3
1 .10
4
Cpul [nF]
t
pul
s
e
[
s]
R
PUL
= 100k
R
PUL
= 47k
R
PUL
= 20k
L6235
16/25
NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION
The L6235 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-to-
Output and Output-to-Ground short circuit protection as well. With this internal over current detection, the exter-
nal current sense resistor normally used and its associated power dissipation are eliminated. Figure 17 shows
a simplified schematic for the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each High Side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current reaches the detection threshold (typically I
SOVER
= 5.6A) the OCD compar-
ator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a
C or to shut down the Three-Phase Bridge simply
by connecting it to pin EN and adding an external R-C (see R
EN
, C
EN
).
Figure 17. Overcurrent Protection Simplified Schematic
Figure 18 shows the Overcurrent Detetection operation. The Disable Time t
DISABLE
before recovering normal
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by C
EN
and R
EN
values and its magnitude is reported in Figure 19. The Delay Time t
DELAY
before turn-
ing off the bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported
in Figure 20.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should
be chosen according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
to 180K
. Recommended values for R
EN
and C
EN
are respectively 100K
and 5.6nF that allow obtaining 200
s Disable Time.
+
OVER TEMPERATURE
I
REF
I
REF
I
1
+I
2
/ n
I
1
/ n
HIGH SIDE DMOS
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOS
HIGH SIDE DMOS
OUT
1
OUT
2
VS
A
OUT
3
VS
B
I
1
I
2
I
3
I
2
/ n
I
3
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40
TYP.
C
EN
R
EN
DIAG
EN
V
DD
C or LOGIC
D02IN1381
17/25
L6235
Figure 18. Overcurrent Protection Waveforms
Figure 19. t
DISABLE
versus C
EN
and R
EN
.
Figure 20. t
DELAY
versus C
EN
.
I
SOVER
I
OUT
V
th(ON)
V
th(OFF)
V
EN(LOW)
V
DD
t
OCD(ON)
t
D(ON)EN
t
EN(FALL)
t
EN(RISE)
t
DISABLE
t
DELAY
t
OCD(OFF)
t
D(OFF)EN
V
EN
=V
DIAG
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1383
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[ n F ]
t
DISA
BLE
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
1
1 0
1 0 0
1
1 0
1 0 0
1
.
1 0
3
C
E N
[ n F ]
t
DISA
BLE
[
s
]
R
E N
= 2 2 0 k
R
E N
= 1 0 0 k
R
E N
= 4 7 k
R
E N
= 3 3 k
R
E N
= 1 0 k
1
10
100
0.1
1
10
Cen [nF]
t
d
el
ay
[
s]
L6235
18/25
APPLICATION INFORMATION
A typical application using L6235 is shown in Figure 21. Typical component values for the application are shown
in Table 3. A high quality ceramic capacitor (C
2
) in the range of 100nF to 200nF should be placed between the
power pins VS
A
and VS
B
and ground near the L6235 to improve the high frequency filtering on the power supply
and reduce high frequency transients generated by the switching. The capacitor (C
EN
) connected from the EN
input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two
current sensing inputs (SENSE
A
and SENSE
B
) should be connected to the sensing resistor R
SENSE
with a trace
length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/
dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5V (High
Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and
Signal Ground separated on PCB.
Table 3. Component Values for Typical Application.
Figure 21. Typical Application
C
1
100F
R
1
5K6
C
2
100nF
R
2
1K8
C
3
220nF
R
3
4K7
C
BOOT
220nF
R
4
1M
C
OFF
1nF
R
DD
1K
C
PUL
10nF
R
EN
100K
C
REF1
33nF
R
P
100
C
REF2
100nF
R
SENSE
0.3
C
EN
5.6nF
R
OFF
33K
C
P
10nF
R
PUL
47K
D
1
1N4148
R
H1
, R
H2
, R
H3
10K
D
2
1N4148
VREF
+
-
BRAKE
14
5
18
19
21
16
OUT
1
H
1
H
2
H
3
GND
RCOFF
OUT
3
OUT
2
VS
A
POWER
GROUND
SIGNAL
GROUND
+5V
+
-
V
S
8-52V
DC
13
VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
R
SENSE
20
BRAKE
6
7
DIAG
EN
C
EN
R
EN
ENABLE
2
FWD/REV
FWD/REV
11
TACHO
8
12
1
23
24
4
17
3
15
22
SENSE
B
THREE-PHASE MOTOR
C
OFF
R
OFF
R
H1
R
H2
R
H3
10
C
REF1
R
2
R
3
R
1
R
DD
R
4
C
3
C
REF2
RCPULSE
9
C
PUL
R
PUL
D02IN1357
M
V
REF
5V
HALL
SENSOR
19/25
L6235
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Figure 22 is shown the approximate relation between the output current and the IC power dissipation using
PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which
package should be used and how large must be the on-board copper dissipating area to guarantee a safe op-
erating junction temperature (125C maximum).
Figure 22. IC Power Dissipation versus Output Power.
THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking con-
figuration for the application is required to maintain the IC within the allowed operating temperature range for
the application. Figures 23, 24 and 25 show the Junction-to-Ambient Thermal Resistance values for the
PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6cm
2
dissipating footprint (copper thickness of 35
m), the R
th(j-amb)
is about 35C/W. Figure 26 shows
mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance
can be reduced down to 15C/W.
Figure 23. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
No PWM
f
SW
= 30 kHz (slow decay)
Test Condition s:
Supply Voltage = 24 V
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
P
I
OUT
[A]
D
[W]
I
OUT
I
1
I
3
I
2
I
OUT
I
OUT
13
18
23
28
33
38
43
1
2
3
4
5
6
7
8
9
10
1 1
1 2
13
W ith o ut G ro u nd La yer
W ith Gr o un d La yer
W ith Gr o un d La yer + 16 via
H o le s
s q . c m
C / W
On-Board Copper Area
L6235
20/25
Figure 24. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 25. SO24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 26. Mounting the PowerSO Package.
39
40
41
42
43
44
45
46
47
48
49
1
2
3
4
5
6
7
8
9
10
11
12
C o p pe r Are a is o n Bo tto m
S id e
C o p pe r Are a is o n To p S i de
s q . cm
C / W
On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
1
2
3
4
5
6
7
8
9
10
11
12
C o pp er A re a is o n T op S id e
s q. cm
C / W
On-Board Copper Area
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
21/25
L6235
Figure 27. Typical Quiescent Current vs.
Supply Voltage
Figure 28. Normalized Typical Quiescent
Current vs. Switching Frequency
Figure 29. Typical Low-Side R
DS(ON)
vs. Supply
Voltage
Figure 30. Typical High-Side R
DS(ON)
vs.
Supply Voltage
Figure 31. Normalized R
DS(ON)
vs.Junction
Temperature (typical value)
Figure 32. Typical Drain-Source Diode Forward
ON Characteristic
4 .6
4 .8
5 .0
5 .2
5 .4
5 .6
0
10
2 0
3 0
40
5 0
6 0
Iq [m A ]
V
S
[V ]
f
sw
= 1kHz
T
j
= 25C
T
j
= 85C
T
j
= 125C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0
20
40
60
80
100
Iq / (Iq @ 1 kHz)
f
SW
[kHz]
0.276
0.280
0.284
0.288
0.292
0.296
0.300
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.336
0.340
0.344
0.348
0.352
0.356
0.360
0.364
0.368
0.372
0.376
0.380
0
5
10
15
20
25
30
R
DS(ON)
[
]
V
S
[V]
T
j
= 25C
0.8
1.0
1.2
1.4
1.6
1.8
0
20
40
60
80
100
120
140
R
DS(ON)
/ (R
DS(ON)
@ 25 C)
T j [C ]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
700
800
900
1000
1100
1200
1300
I
SD
[A]
V
SD
[mV]
T
j
= 25C
L6235
22/25
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.60
0.141
a1
0.10
0.30
0.004
0.012
a2
3.30
0.130
a3
0
0.10
0
0.004
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D (1)
15.80
16.00
0.622
0.630
D1
9.40
9.80
0.370
0.385
E
13.90
14.50
0.547
0.570
e
0.65
0.0256
e3
11.05
0.435
E1 (1)
10.90
11.10
0.429
0.437
E2
2.90
0.114
E3
5.80
6.20
0.228
0.244
E4
2.90
3.20
0.114
0.126
G
0
0.10
0
0.004
H
15.50
15.90
0.610
0.626
h
1.10
0.043
L
0.80
1.10
0.031
0.043
N
10
(max.)
S
8
(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
23/25
L6235
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.320
0.170
A1
0.380
0.015
A2
3.300
0.130
B
0.410
0.460
0.510
0.016
0.018
0.020
B1
1.400
1.520
1.650
0.055
0.060
0.065
c
0.200
0.250
0.300
0.008
0.010
0.012
D
31.62
31.75
31.88
1.245
1.250
1.255
E
7.620
8.260
0.300
0.325
e
2.54
0.100
E1
6.350
6.600
6.860
0.250
0.260
0.270
e1
7.620
0.300
L
3.180
3.430
0.125
0.135
M
0 min, 15 max.
Powerdip 24
A1
B
e
B1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DATA
L6235
24/25
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D
(1)
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0;75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
0 (min.), 8 (max.)
ddd
0.10
0.004
(1) "D" dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
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