L6238S

12V SENSORLESS SPINDLE MOTOR CONTROLLER

PRODUCT PREVIEW

12V OPERATION
3A, THREE-PHASE DMOS OUTPUT
(TOTAL R

dson

0.52

)

NO HALL SENSORS REQUIRED
DIGITAL BEMF PROCESSING
LINEAR OR PWM CONTROL
STAND ALONE OR EXT. DRIVER
SHOOT-THROUGH PROTECTION
THERMAL SHUTDOWN

DESCRIPTION
The L6238S is a Three-Phase, D.C. Brushless
Spindle Motor Driver system. This device features
both the Power and Sequence Sections.
Higher Power Applications can be activied with
the addition of an external Linear Driver, or by op-
erating the Internal Drivers in PWM.
Motor Start-Up, without the use of Hall Sensors,
can be achieved either by an internal start-up al-
gorithm or by manually sequencing the Output
Drivers, using a variety of User-Defined Start-UP
Algorithms.

Protection features include Stuck Rotor\Backward
Rotation Detection and Automatic Thermal Shut-
down.

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

October 1995

ZERO

CROSSING

DETECTOR

ALIGN + GO

START-UP

ONE-SHOT

SLEW-CTRL

PWM

LIN

THERMAL

SHUTDOWM

OT-WARN

CHARGE

PUMP

CPUMP3

CPUMP1

CPUMP2

D95IN232

BIAS

POWER

STAGE

AV=4V/V

DIGITAL

DELAY

OUT B

OUT C

CTR TAP

CSA INPUT

GND

PWM

TIM

VANALOG

BEMF

SENSE

VPOWER

BRAKE
DELAY

RSENSE1

DRV

CNTL

TDLY(0)

CSA

OUT A

GATE DRIVE

GM COMP

SYSTEM

CLOCK

SYS CLOCK

RSENSE2

VCTRL

PWM

COMP

PWM/

SLEW

SEQUENCER

FALIGN

OUTPUT

ENABLE

RUN/

BRAKE

SEQ INCR

MONO/SEQ

CTRL

TDLY(1)

TDLY(2)

MONO

DET

MASK DLY

TOGGLE

DIVIDE

BY N

SPIN

SENSE

FMTR

SEL POL

BLOCK DIAGRAM

ORDERING NUMBERS: L6238S (PLCC44)

L6238SQA (PQFP44)
L6238SQT (TQFP64)

PLCC44

PQFP44

TQF P64

1/31

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

dss

Output Brakdown Voltage

Power

Motor Supply Voltage

Logic

Logic Supply Voltage

Analog

Analog Supply Voltage

Input Voltage

-0.3 to 7

storage

Charge Pump Storage Capacitor

4.7

�

mdc

Motor Current (DC) (TQFP64 only)

(PLCC44 and PQFP44)

2.5

A
A

mpk

Peak Motor Current (Pulsed: T

= 5ms, d.c. = 10%)

tot

Power Dissipation at Tamb = 50

�

C (PLCC44)

(TQFP64)
(PQFP44)

2.3
1.7
1.3

W
W
W

Storage and Junction Temperature

-40 to 150

�

THERMAL DATA

Symbol

Parameter

PLCC44

PQFP44

TQFP64

Unit

th (j-amb)

Thermal Resistance Junction-Ambient

�

C/W

Those Thermal Data are valid if the package is mounted on Mlayer board in stillair

44 43

24 25

OUTPUT

SPIN

SENSE

BRAKE

DELAY

CHARGE

PUMP

GND

RSENSE

GND

MASK

DELAY

VPOWER

PWM/SLEW

CENTER

TAP

GND

CHARGE PUMP 1

CHARGE PUMP 3

OUTPUT A

VANALOG

VPOWER

N.C.

TDLY(0)

TDLY(1)

TDLY(2)

GND

GATE DRIVE

GM COMP

OUTPUT C

CSA INPUT

RSENSE 2

VCONTROL

N.C.

FMOTOR

VLOGIC

GND

RUN/BRAKE

OUTPUT

ENABLE

PWM/LINEAR

SELECT

POLE

OTWARN

PWM

LIMIT

TMR

PWM

COMP

FALIGN

MONO/SEQINC

CTRL

SEQ.

INCREMENT

SYSTEM

CLOCK

D95IN245

PIN CONNECTION PLCC44 (Top view)

L6238S

2/31

44 45

OUTPUT

N.C.

VPOWER

VANALOG

VPOWER

GND

CHARGE

PUMP

CHARGE

PUMP

N.C.

OTWARN

SELECT POLE

PWM LIMIT TMR

OUTPUT ENABLE

PWM/LINEAR

RUN/BRAKE

SEQ. INCREMENT

SYSTEM CLOCK

MONO/SEQINC CTRL

FALIGN

CHARGE PUMP 2

RSENSE 1

BRAKE DELAY

OUTPUT B

SPIN SENSE

OUTPUT B

PWM/SLEW

CENTER TAP

VPOWER

OUTPUT

N.C.

RSENSE

CSA

INPUT

RSENSE

GND

COMP

GATE

DRIVE

D95IN244

PWM COMP

N.C.

GND

MASK DELAY

GND

N.C.

GND

TDLY(0)

TDLY(1)

GND

TDLY(2)

VCONTROL

FMOTOR

GND

VLOGIC

PIN CONNECTION TQFP64 (Top view)

29 30

VANALOG

N.C.

TDLY(0)

TDLY(2)

GND

TDLY(1)

GND

CHARGE

PUMP

CHARGE

PUMP

VPOWER

OUTPUT

OTWARN

SELECT POLE

PWM LIMIT TIMER

PWM/LINEAR

RUN/BRAKE

OUTPUT ENABLE

SEQ. INCREMENT

SYSTEM CLOCK

MONO/SEQINC CTRL

FALING

PWM COMP.

GND

CHARGE PUMP 2

RSENSE 1

BRAKE DELAY

OUTPUT B

SPIN SENSE

PWM/SLEW

CENTER TAP

VPOWER

MASK/DELAY

GND

CSA

INPUT

VCONTROL

N.C.

VLOGIC

GND

FMOTOR

GND

GATE

DRIVE

COMP

RSENSE

OUTPUT

D95IN243

PIN CONNECTION PQFP44 (10x10) (Top view)

L6238S

3/31

PIN FUNCTIONS

PLCC44 PQFP44 TQFP64

Name

I/O

Function

56, 57

OUTPUT B

I/O

DMOS Half Bridge Output and Input B for Bemf sensing.

SPIN SENSE

Toggless at each Zero Crossing of the Bemf.

BRAKE DELAY

Energy Recovery time constant, defined by external R-C to ground.

60, 61

sense 1

Outputs A+B connections for the Motor Current Sense Resistor
to ground

CHARGE

PUMP 2

Negative Terminal of Pump Capacitor.

6, 7,

17, 29,

39, 40

1, 11,

23, 33,

34, 44

GROUND

Ground terminals.

CHARGE PUMP 1

Positive terminal of Pump Capacitor.

CHARGE PUMP 3

Positive terminal of Storage Capacitor.

6, 7

OUTPUT A

I/O

DMOS Half Bridge Output and Input A for Bemf sensing.

11, 42

5, 36

9, 10,

52, 53

power

Power Section Supply Terminal.

analog

12V supply.

13, 32

7, 26

8, 18,

19, 31,

N.C

Open Terminal

Tdly(0)

Three bits that set the Delay between the detection of the Bemf
zero crossing, and the commutation of the next Phase.

Tdly(1)

Tdly(2)

OTWARN

Overtemperature Warning Output

SELECT POLE

Selects # of Motor Poles. A zero selects 8, while a one selects 4
poles.

PWM TIMER

Capacitor connected to this pin sets the maximum time allowed
for 100% duty cycle during PWM operation

PWM/LINEAR

Selects PWM or Linear Output Current Control

OUTPUT

ENABLE

Tristates Power Output Stage when a logic zero.

SEQUENCE

Rising edge will initiate start-up. A Braking rountine is started
when this input is brought low.

SEQ

INCREMENT

A low to high transition on this pin increments the Output State
Sequencer.

SYSTEM CLK

Clock Frequency for the system timer/counters.

MONO/SEQ.

INC. CONTROL

A logic one will disable the Monotonicity Detector and Sequence
Increment functions.

Falign

Reference Frequency for the opt. Auto-Start Algorithm. If int.
start up is not used, this pin must be connected to the System
Clock.

PWM COMP

Output of the PWM Comparator

Vlogic

5V Logic Supply Voltage.

Fmotor

Motor Once-per-Revolution signal.

Vcontrol

Voltage at this input controls he Motor Current

CSA INPUT

Input to the Current Sense Amplifier.

39, 40

Rsense 2

Output C connection for the Motor Current Sense Resistor to
ground.

42, 43

OUTPUT C

I/O

DMOS Half Bridge Output and Input C for Bemf sensing.

gm COMP

A series RC network to ground that defines the compensation of
the Transconductance Loop.

L6238S

4/31

PIN FUNCTIONS

PLCC44 PQFP44 TQFP64

Name

I/O

Function

GATE DRIVER

I/O

Drivers the Ext. PFET Gate Driver for Higher Power applications.
This pin must be grounded if an external driver is not used.

MASK/DELAY

Internal Logic Signals used for production Testing

CENTER TAP

Motor Center Tap used for differential BEMF sensing.

PWM/SLEW

R/C at this input set the Linear Slew Rate and PWM OFF-Time

0.0

0.3

1.0

3.0

Cb(

�

0.0

0.3

1.0

3.0

(s)

D95IN274

Figure 1: Brake Delay Timeout vs C

brake

= 1Meg)

100

300

Rs(K

)

0.0

0.3

1.0

3.0

(V/

�

D95IN275

Figure 2: Linear Slew Rate vs R

slew

100

300

Coff(pF)

PWM

(

�

D95IN276

Figure 3: PWM Off - Time vs R

slew

off

100

300

Ctimer(pF)

PWM

(

�

D95IN277

Figure 4: PWM Limit Time - Out vs C

timer

L6238S

5/31

ELECTRICAL CHARACTERISTICS (T

amb

= 0 to 70

�

C; V

= V

Pwr

= 12V; V

logic

= 5V; unless otherwise

specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

GENERAL

analog

Analog Supply Voltage

10.5

13.5

analog

Analog Supply Current

Run Mode V

= 13.5V

1.5

2.7

4.5

Brake Mode V

= 13.5V

280

800

�

logic

Logic Supply Voltage

4.5

5.0

5.5

log ic

Logic Supply Current

Run Mode V

logic

= 5.5V

3.2

Brake Mode

100

500

1000

�

THERMAL SHUTDOWN

* T

Shut Down Temperature

150

180

�

* T

hys

Recovery Temperature
Hysteresis

�

* T

Early Warning Temperature

-25

�

POWER STAGE

DS(on)

Output ON Resistance per FET

= 25

�

C; V

= 10.5V

= 125

�

C; V

= 10.5V

0.20

0.26
0.40

o(leak)

Output Leakage Current

pwr

= 15V

Body Diode Forward Drop

= 2.0A

1.5

dVo/dt

Output Slew Rate (Linear)

slew

= 100K

0.15

0.30

0.45

�

Output Slew Rate (PWM)

150

�

Gate Drive for Ext. Power
DMOS

control

= 1V; V

sns

= 0V;

= 10.5V

4.5

Gate-Drive

Ext Driver Disable Voltage

0.7

Ctrl-Range

Voltage Control Input Range

5.0

in(VCtrl)

Voltage Control Input Current

�

PWM OFF-TIME CONTROLLER (R

slew

= 100K

, C

off

= 120pF)

off

OFF Time

�

chrg

Capacitor Charge Voltage

= 10.5V

2.31

2.65

3.1

trip

Lower Trip Threshold

1.25

PWM LIMIT TIMER

chrg

Capacitor Charge Current

PWM Timer

= 0V; V

= 10.5V

10.0

20.0

�

chrg

Capacitor Charge Voltage

= 10.5V

3.0

3.5

4.0

trip

Lower Trip Threshold

100

400

BEMF AMPLIFIER

inCT

Center Tap Imput Impedance

Bemf

Minimum Bemf (Pk-Pk)

CURRENT SENSE AMPLIFIER

snsin

Input Bias Current

= 13.5V

�

Voltage Gain

3.8

4.0

4.2

V/V

Slew Rate

0.33

0.8

�

L6238S

6/31

ELECTRICAL CHARACTERISTICS (Continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

BRAKE DELAY

chrg

Capacitor Charge Voltage

= 50K

8.8

9.6

10.5

Input Current

= 5.0V

500

out3

Source Current

= 10.5V

0.5

Thres

Delay Timer Low Trip Threshold

1.2

1.8

2.8

CHARGE PUMP

out

Storage Capacitor Output
Voltage

= 10.5V; I

out

= 500

�

Charge Pump Frequency

140

450

KHz

Vstorage Input Current (Run
Mode)

storage

= 12V; V

= V

logic

= 0

�

brkdly

Vstorage Leakage Current
(Brake Delay Mode)

storage

= 12V; V

= V

logic

= 0

0.4

�

brake

Vstorage Leakage Current
(Brake Mode)

storage

= 12V; V

= V

logic

= 0

0.1

�

SEQUENCE INCREMENT

seq

Time Between Rising Edges

�

OUTPUT TRANSCONDUCTANCE AMPLIFIER Note: Measure at OTA Comp. pin.

Voltage Output High

= 10.5V

outL

Output Voltage

2.0

source

Output Voltage

40.0

0.5

sink

Output Sink Current

40.0

�

LOGIC SECTION

inH

inL

Input Voltage (All Inputs
Except Run/Brake

logic

= 4.5 to 5.5V

3.5

1.5

V
V

inH

inL

Run/Brake Input Voltage

logic

= 4.5 to 5.5V

2.0

1.0

V
V

inH

inL

Input Current

-1.0

1.0

�

outL

inL

Output Voltage

Vsink = 2.0mA
V

source

= 2.0mA

4.5

0.5

V
V

sys

System Clock Frequency

8.0

12.0

MHz

off

Clock ON/OFF Time

Tdelay (2)

Tdelay (1)

Tdelay (0)

Commutation Phase Delay,

in Electrical Degrees

2.0

9.4

18.80

20.68

22.56

24,44 (*)

26.32

28.20

(*) Input Default

Phase Delay Truth Table

L6238S

7/31

FUNCTIONAL DESCRIPTION
1.0 INTRODUCTION

1.1 Typical Application
In a typical application, the L6238S will operate in
conjunction with the L6244 Voice Coil Driver as

shown in Fig. 1-1.
This configuration requires a minimum amount of
external components.
1.2 Input Default States
Figure 1-2 depicts the two possible input struc-
tures for the logic inputs. If a particular pin is not

OUT

CTR

TAP

OUT

RSENSE

4.35

CSA

6.33

10nF

CHRG

PUMP

CHRG

PUMP

8.12MHz

4.7

�

CHRG

PUMP

SYS

CLK

�

ALIGN

PWR

11,42

400pF

PWM

SLEW

100K

10K

0.068

�

COMP

0.1

�

BRK

DLY

6,7,17,

29,39,40

GND

60-90Hz

Note:

the

internal

Start-up

Algorithm

not

used,

connect

this

SYS_CLK

ANLG

12V

LOGIC

VLOGIC(5V)

L6238S

SPINDLE

MOTOR

DRIVER

CONTROLLER

220pF

GATE

DRV

MONO

SEQ.

OUT

ENA

RUN/BRK

CTRL

SEQ

INC

MTR

WARM

DLY(0)

DLY(1)

DLY(2)

PWM

TMR

data(0)

data(1)

data(2)

data(3)

data(4)

data(5)

data(6)

data(7)

10K

LOGIC

POR

GATE

DRIVE

Vpower

�

0.068

�

3.6K

27K

0.1

�

VCM

0.4

360K

10K

100K

6,7,17,29,39,40

GND

POR

DLY

Rprogram

PROG

CC/2

GAIN2-IN

DA0Out

GAIN1-IN

ERROR

AMP

OUTPUT

PUMP

CP2

CP1

0.01

�

D95IN278

L6244

VOICE

COIL

DRIVER

DA2

OUT

SENSE

OUT

SENSE

+INPUT

SENSE

-INPUT

OUT

SENSE

Figure 1-1

L6238S

8/31

used in an application, it may either be connected
to ground or VLOGIC as required, It may also be
simply left unconnected.
If no connection is made, the pin is either pulled
high or low by internal constant current gener-
ators as shown above.

A listing of the logic and clock inputs is shown in
Table 1 with the corresponding default state.

1.3 Modes of Operation
There are 5 basic modes of operation.
1) Tristate

When Output Enable is low, the output power
drivers are tristated.
2) Start-Up
With Output Enable high, bringing Run/Brake
from a low to a high will energize the motor and
the system will be driven by the Fully-Integrated
StartUp Algorithm.
A user-defined Start-Up Algorithm, under control
of a MicroProcessor, can also be achieved via the
sequence increment input.

3) Run
Run mode is achieved when the motor speed
(controlled

the

external

microprocessor)

reaches the nominal speed.

4) Park
When Run/Brake is brought low, energy to park
the heads may be derived from the rectified Bemf.
The energy recovery time is a function of the
Brake Delay Time Constant. In this state, the qui-
escent current of the device is minimized (sleep
mode).
5) Brake
After the Energy Recovery Time-Out, the device
is in Brake, with all lower Drivers in full conduc-
tion.

There are two mutually exclusive conditions
which may be present during the Tristate Mode
(wake up):

a)the spindle is stopped.
b)the system is still running at a speed that

allows for resynchronization.

In order to minimize the ramp up time, the micro-
controller has the possibility to:

check the SPIN SENSE pin, (which toggles at
the Bemf zero crossing frequency)
enable the power to the motor based on the
previous information. Otherwise the

�

P may is-

sue a Brake command, followed by the start-
up procedure after the motor has stopped spin-
ning.

2.0 STATE DIAGRAMS
2.1 State Diagram
Figure 2-1 is a complete State Diagram of the
controller depicting the operational flow as a func-
tion of the control pins and motor status. The flow
can be separated into four distinct operations.

2.2 Align + Go

Figure 2-2 represent the normal flow that will
achieve a spin-up of the spindle motor using the
internally generated start up algorithm.
Upon

power

up,

from

any

state

with

Run/Brake low the controller first sets the state
machine for State=1 with the Outputs Tristated.

The period counter that monitors the time be-
tween zero crossing is stopped, analog with the
phase and mask delay counters.
When Run/Brake is brought high, the motor is in
the first part of the align mode at State 2 (Output
A high and Output C low). If Output Enable is
high, the controller first checks to determine if the
motor is still spinning for a time of 21

(with

Sys_Clk = 10MHz). The drivers are now enabled
and after the align time-out, (64/Falign), the se-
quencer double increments the outputs to State 4
(Output B high and Output A low). The first part
of this align mode is used to reduce the effects of
stiction

Pin Function

Configuration

Tdly (0,1,2)

Pull-Down

Select Pole

Pull-Down

PWM/Linear

Pull-Down

Output Enable

Pull-Down

Run/Brake

Pull-Up

Sequence Increment

Pull-Down

System Clock

Pull-Up

Faling

Pull-Up

Table 1

330

LOGIC

�

330

LOGIC

�

PULL-UP

PULL-DOWN

D95IN279

Figure 1-2

L6238S

9/31

After the next align time-out 192/Falign), the con-
troller enters the Go mode, were the sequencer
again double increments the output phase upon
detection of the motor's Bemf.
The align time-out may be optimized for the appli-
cation by changing the Faling reference fre-
quency.
A Watch-Dog Timer protection feature is built into
the control logic to monitor the Falign pin for a
clocking signal. This circuitry, shown in Figure 2-3
will prevent start up the device if the Falign clock
is not present.

Without this feature, the output would remain in
the first phase under high current conditions, if
the clock were not present.
If the external sequencer is used to provide start
up, the system clock may be tied to the Falign pin
to satisfy the requirements of the Watch-Dog
Timer.

2.3 Resynchronization
If power is momentarily lost, the sequencer can
automatically resynchronize to the monitored

STATE = 1
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
MASK STOP

SEQLNC=1 &
OUTENA=0
RUN/BRK=X

INT. START-UP DISABLED
MIN. CLOCK DELAY
LOAD MIN. DELAY
LOAD MIN. MASK***

RUN/BRK=1 &
OUTENA=1

DRIVERS ON
PERIOD COUNT
DELAY COUNT

STATE=STATE+1*
MASK COUNT

MASK COUNT

SEQINC=0

SEQINC=1

LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT**

BEMF

SEQINC=0

SEQINC=1

RUN/BRAKE=1

RUN/BRAKE=0
FROM ANY STATE

DRIVERS OFF
MIN CLOCK DELAY
LOAD MIN MASK***
PERIOD STOP
DELAY COUNT
STATE=STATE+1
MASK COUNT

LOAD MIN. DELAY
LOAD MIN. MASK***
DELAY COUNT
STATE=STATE+1
MASK COUNT

BEMF

STATE=STATE+1

SEQINC=1

RETURN TO

PREVIOUS STATE

(CHANGING SEQINC=1)

BEMF

FROM ANY STATE
WITH SEQ_INC=0

* VALID IF SEQINC=0, AND DELAY TIMES OUT
** CLOCK DELAY=F(TDLY_[2:0])

WHEN BEMF PERIOD <3.3ms @ 10MHz
(SPEED >12.7Hz FOR 8 POLES)

STATE=STATE+2

CHECK FOR Zc

BEMF

DRIVERS OFF
STATE=STATE+1
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MAX MASK
DELAY COUNT
STATE=STATE+1
MASK COUNT

OUTENA=1

DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP

DRIVERS ON
PERIOD STOP
DELAY STOP
MASK STOP

STATE=STATE+2

STATE=STATE+1
LOAD DELAY=MIN
LOAD MASK=MAX
PERIOD COUNT
DELAY COUNT
STATE=STATE+1
MASK COUNT

BEMF

LOAD DELAY=MIN
LOAD MASK=MIN
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT

SYS_CLK

DRIVERS OFF

RUN/BRK=0

DRIVERS OFF

RUN/BRK=0

DRIVERS ON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT

DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP

OUTENA=0

BEMF

MONO=0**

BEMF

OUTENA=1

BEMF

ALIGN &
GO MODE

RESYNCHRONIZATION
MODE

RUN

MODE

* CLOCK DELAY=F(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES)
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF1: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
**MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE)
***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2

�

D95IN280

192/FALIGN

64/FALIGN

OUTENA=0

SYS_CLK

OUTENA=0

OUTENA=1

BEMF

POR=0
FROM ANY STATE
(FOR IS GENERATED INTERNALLY
BY MONITORING VLOGIC)

Figure 2-1

L6238S

10/31

Bemf. This resychronization can either occur
whenever Output Enable or Run/Brake is first
brought low then high.
Referring to figure 2-4, the "Hold for Resync"
state is brought low. The controller leaves this
state and enters "Start Resync" when Output En-
able is high.

TO START-UP
LOGIC

OVER TEMP SHUTDOWN

D95IN311

OUTPUT

ENABLE

RUN/

BRAKE

FALIGN

Figure 2.3: Watch-Dog Timer

LOAD MIN DELAY
LOAD MIN MASK***
DELAY COUNT
STATE=STATE+1
MASK COUNT

LOAD DELAY=MIN
LOAD MASK=MIN
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT

CHECK FOR Zc

OUTENA=1

BEMF

DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP

D95IN312

*CLOCK DELAY=(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES)
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
** MONO=0 WHEN FREQ (BEMF)=2*FREQ(PHASE)
*** MIN MASK=192/SYS_CLK(I.E.WITH SYS_CLK=10MHz, MIN MASK=19.2

�

BEMF

RUN/BRK=0

BEMF

DRIVERS OFF

DRIVERS ON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAYH COUNT*
STATE=STATE+1
MASK COUNT

MONO=0**

BEMF

RUN
MODE

OUTENA=0

OUTENA=1

HOLD FOR RESYNC

RESYNCHRONIZATION MODE

Figure 2-4

STATE=1
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
MASK STOP

DRIVERS OFF
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MIN MASK
PERIOD STOP
DELAY COUNT
STATE=STATE+1
MASK COUNT

CHECK FOR Zc

DRIVERS ON
PERIOD STOP
DELAY STOP
MASK STOP

STATE=STATE+1
LOAD DELAY=MIN
LOAD MASK=MAX
PERIOD COUNT
DELAY COUNT
STATE=STATE+1
MASK COUNT

CHECK FOR Zc

BEMF

SYS_CLK

RUN/BRAKE=1

POR=0
FROM ANY STATE

OUTENA=1

64/FALIGN

192/FALIGN

DRIVERS ON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT

BEMF

D95IN310

BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
***MIN MASK=192/SYS_CLK (I.E. WITH SYS_CLK=10MHz, MIN MASK=19.2

�

BEMF

RUN/BRK=0
FROM ANY STATE

Figure 2.2

L6238S

11/31

If zero crossings are detected, the sequencer will
automatically lock on to the proper phase.
This resynchronization will take effect with the
motor speed running as low as typically 30% of
it's nominal value.

2.5 External Sequencing
Although the user-defined Start-Up Algorithm is
flexible and will consistently spin up a motor with
no external interaction, the possibility exists
where certain applications might require complete
microprocessor control of start-up.
The L6238S offers this capability via the SE-
QUENCE INCREMENT input. Referring to figure
2-5, during initial power-up with Output Enable
low, the controller is in the "Hold and Wait for De-
cision" state. If the SEQUENCE INCREMENT pin
is brought high during this state, the Auto StartUp
Algorithm is disabled and the sequencer can be
controlled externally.
When Output Enable and Run/Brake are
brought high, the sequencer is incremented on
each positive transition o the SEQUENCER IN-

CREMENT pin. During the time that this pin is
high, all Bemf information is masked out. When it
is low, the Bemf information can be detected nor-
mally after the internal mask time. The minimum
mask time is 192/Sys_Clk (i.e. with Sys_Clk =
10MHz, min. mask = 19.2

�

s) Therefore to insure

that the sequencer is under complete control of
the state machine, the time that the SEQUENCE
INCREMENT pin is held low should be much less
then the min. mask time, but greater then 1

�

When the motor has reached a predetermined
speed, the SEQUENCE INCREMENT pin can be
left low and the L6238S Motor Control logic will
take over and automatically spin up the motor to
the desired speed

.
3.0 START-UP ALGORITHMS
3.1 Spin-Up Operation
The spin operation can be separated into 3 parts:
1) Open Loop Start-Up - The object is to create
motion in the desired direction so that the Bemf
voltages at the 3 motor terminals can provide reli-
able information enabling a transition to closed
loop operation.

STATE=1
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
MASK STOP

INT START-UP DISABLED
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MIN MASK

MASK COUNT

SEQINC=1 &
OUTENA=0
RUN/BRK=X

D95IN313

*VALID IF SEQINC=0, AND DELAY TIMES OUT
**CLOCK DELAY=F(TDLY_[2:0])

WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES)

SEQINC=0

STATE=STATE+1
MASK COUNT

LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT**

BEMF

POR=0
FROM ANY STATE

DRIVERS ON
PERIOD COUNT
DELAY COUNT

SEQINC=0

BEMF

SEQINC=1

STATE=STATE+1

SEQINC=1

FROM ANY STATE

WITH SEQ_INC=0

RETURN TO

PREVIOUS STATE

(CHANGING SEQINC=1)

RUN/BRK=1 &
OUTENA=1

SEQINC=1

Figure 2-5

L6238S

12/31

2) Closed Loop Start-Up - The Bemf voltage
zerocrossings provide timing information so that
the motor can be accelerated to steady state
speed.
3) Steady-State Operation - The Bemf voltage
zero-crossings provide timing information for pre-
cision speed control.
The L6238S contains features that offer flexible
control over the start-up procedure. Either the on-
board Auto-Start Algorithm can be used to control
the start-up sequence or more sophisticated ex-
tenal start-up algorithms can be developed using
the Serial Port and key control/sense functions
brought out to pins.

3.2 Auto-Start Algorithm
When initially powered up, the controller defaults
to the internal AutoStart Mode. When Run/Brake
is low, the L6238S is in brake mode, and the
Auto-Start Algorithm is reset. In the brake mode,
all of the lower DMOS drivers are ON, and the up-

per drivers are OFF.

The Auto-Start Algorithm is based on an Align &
Go approach and can be visualized by referring to
Figure 3-1. Shown are the Run/Brake control sig-
nals, sequencer function, and the three output
voltage waveforms.

Referring to figure 3-1, the following is the se-
quence of events during Auto-Start:
With Output Enable = 1, Run/Brake = 0

- State Machine is set to State 1 with the drivers

Trisatted.

Alignment Phase (1)

Run/Brake = 1

- Output Stage is sequenced to State 2 and the

drivers energized with OUTPUT A high and
OUTPUT C low for 64/Falign seconds.

Alignment Phase (2)

- Output Stage is double sequenced to State 4

with OUTPUT B high and OUTPUT A low for

STATE 2

A=HIGH

B=FLOAT

C=LOW

STATE 4

A=LOW

B=HIGH

C=FLOAT

STATE 6

A=FLOAT

B=LOW

C=HIGH

500ms/DIV

* FALIGN=90Hz

OUT

10V

OUT

10V

OUT

10V

ALIGNMENT

DOUBLE INCREMENTS

*0.711s

*2.133s

RUN/BRAKE

SEQUENCER

D95IN314

Figure 3-1: Align+Go

L6238S

13/31

192/Falign seconds.

- During the alignment phase, the SEQ INCRE-

MENT signal is ignored.

Go Phase

- The internal sequencer double increments the

output stage to State 6, which should produce
torque in the desired direction.

- with SEQ INCREMENT held low, the se-

quencer is now controlled by the Bemf zero
crossings, and the motor should ramp up to
speed.

3.3 Externally Controlled Start-Up Algorithms
Enhanced Start-Up Algorithms can be achieved
by using a

�

Processor to interact with the

L6238S.' The L6238S has the ability to transition
to Closed Loop Start-Up at very low speeds, re-
ducing the uProcessor task to monitoring status
rather than real time interaction. Thus, it is a per-
fect application for an existing

�

Processor.

The following control and status signals allow for
very flexible algorithm development:

SEQ_INCR A low to high transition at this input
is used to increment the state of the power out-
put stage. It is useful during start-up, because
the

�

Processor can cycle to any desired state,

or cycle through the states at any desired rate.
When held high, it inhibits the BEMF zero
crossings from incrementing the internal se-
quencer.

SPIN SENSE This output is low until the first
detected Bemf zero crossing occurs. It then
toggles at each successive zero crossing. This
signal serves as a motion detector and gives
useful timing information as well as the slope
of the Bemf.

3.4 Start Up Approaches
Align & Go Approach The Align & Go approach
provides a very time efficient algorithm by ener-
gizing the coils to align the rotor and stator to a
known phase. This approach can be achieved via
the sequencing SEQ INCR. SPIN SENSE can be
monitored to assure that motion occurred. Once
ample time is given for alignment to occur, SEQ
INCR can be double incremented, and the SPIN
SENSE pin can be monitored to detect motion.
When SEQ INCR is pulled low, control is trans-
ferred to the internal sequencer, and the L6238S
finishes the spinup operation. If no motion is de-
tected, SEQ INCR can be incremented to a differ-
ent phase and the process can be repeated. The
alignment phase may cause backward rotation,
which on the average will be greater than the
Stepper Motor approach.

The Auto-Start algorithm described earlier is an
Align & Go approach. The main advantages of
the integrated Auto-Start are that the

�

P is not in-

volved real-time, and there are a minimum of in-
terface pins required to the spindle control sys-
tem.

Stepper Motor Approach This approach mini-
mizes backward rotation by sequencing SEQ
INCR at an initial rate that the rotor can follow.
Thus, it is driven in a similar fashion to a stepper
motor. The rate is continually increased until the
Bemf voltage is large enough to reliably use the
zero-crossings for commutation timing. SEQ
INCR is held low, causing control to be passed to
the L6238S's internal sequencer as in the Align &
Go approach.

The Stepper Motor approach takes longer than
the Align & Go approach because the initial com-
mutation frequency and subsequent ramp rate
must be low enough so that the motor can follow
without slipping. This implies that to have a reli-
able algorithm, the initial frequency and ramp rate
must be chosen for the worst case motor under
worst case conditions.

4.0 MOTOR DRIVER

4.1 Output Stage
The output stage forms a 3-Phasefull wave bridge
consisting of six Power DMOS FET High output
currents are allowed for bbrief periods. High out-
put currents are allowed for brief periods. Output
Power exceeding the stand-alone power dissipa-
tion capabilities of the L6238S can be increased
with the addition of an external P-FET or by the
use of Pulse-Width-Modulation.

Table 4-1 is a reference diagram that lists the pa-
rameters associated with 8-pole motors operating
at 3600 and 5400 RPM.
Figure 4-1 represents the waveforms associated
with the output stage. The upper portion of figure
4-1 shows the flow of current in the motor wind-
ings for each of the 24 phase increments. A rota-
tional degree index is shown as a reference along
with a base line to indicate the occurrence of a
zero crosing. The output waveforms are a digitally
reproduced voltage signals as measured on sam-
ples.The feedback Input is multiplexed between
the internal Bemf Zero Crossing Detector and an
externally provided sync pulse (EXT INDEX)

Shown in figure 10 is the classical state diagram
for a phase detector along with waveform exam-
ples.
A typical

sequence starts when the outputs

switch states. Referring to figure 4-1, during
phase 1, output A goes high, while outputB is low.
During this phase, output C is floating, and the
Bemf is monitored. The outputs remain in this
state for 60 electrical degrees as indicated by the
first set of dashed lines. After this period the out-

L6238S

14/31

put switched to phase 2 with output A high and C
low with the Bemf amplifier monitoring output B.
In order to prevent commutation current noise be-
ing detectedm as a false zero crossing, a mask-
ing circuit automatically blanks out all incoming
signals as soon as a zero crossing is detected.
When the next commutation occurs an internal
counter starts counting down to set the time that
the masking pulse remains.
The counter is initially loaded with a number that
is equal to time that is always 25% of the previous
phase period or 15 electrical degrees. The time-
out of the masking pulse shown for reference at
the bottom of figure 4-1. Thus the actual masking
period is the total of the time from the detected
zero crossing to the phase commutation, plus
25% of the previous period. The mask pulse op-
eration is further discussed in section 4.6, Slew
Rate Control and PWM operation.
After the masking period, the Bemf voltage at out-
put B is monitored for a zero crossing. Upon de-
tection of the crossing, the output is commutated
after the selected phase delay insuring maximum

torque. The spin sense waveform at the bottom of
the figure indicates that this output signal toggles
with each zero crossing.

4.2 Brake Delay

When Run/Brake is brought low, a brake is initi-
ated. Referring to figure 4-2, SW1 is opened and
the brake delay capacitor, C

brake

, is allowed to

discharge towards groun via R

brake

At the same time, switches SW2 through SW7
bring the gates of the output FETs to ground halt-
ing conduction, causing the motor to coast. While
the motor is coasting, the Bemf is used to park
the heads. When Cbrake reaches a voltage that
is below the turn ON threshold of Q1, Switches
SW8, 9, and 10 bring the gates of the lower driv-
ers to V

brake

potential. This enables the lower

FETs causing a braking action.
The analog and logic supplies are not monitored
in the L6238S, since the L6244 already monitors
this voltage and initiates a Park function when
either supply drops to a predeterminated level.

Figure 4-2

L6238S

16/31

4.3 Charge Pump
The charge pump circuitry is used as a means of
doubling the analog supply voltage in order to al-
low the upper N-channel DMOS transistors to be
driven like P-channel devices. The energy stored
in the reservoir capacitor is also used to drive the
lower drivers in a brake mode if the analog supply
is lost. Figure 4-3 is a simplified schematioc of the
charge pump circuitry.

A capacitor, C

pump

, is used to retrieve energy

from the analog supply and then "pumps" it into
the storage capacitor, C

resvr

An internal 300KHz oscillator first turns ON Q2 to
quickly charge C

pump

to approximately the rail

voltage. The oscillator then turns ON Q1 while
turning OFF Q2. Since the bottom plate of C

pump

is now effectively at the rail voltage via D2.
A zener-referenced series-pass regulator supplies

Figure 4-3

Islew

PUMP

SW2

Cfet

UPPER A

VCTRL

VPOWER

Islew

SW3

Cfet

OUTPUT

OUTA

3.1V

SLEW RATE

REFERENCE CURRENT

SLW

RSENSE

CSA

PWM SLEW/RC

LOWER A

D95IN315

VANALOG

Figure 4-4

L6238S

17/31

a voltage, V

brake

, during brake mode.

The maximum capacitance specified for the Stor-
age Capacitor is 4.7

�

F.For applications requiring

a larger value, an external diode should be con-
nected between Vanalog and the

Storage Ca-

pacitor to prevent excessive inrush current from
damaging the charge pump circuitry. A small
value resistor (i.e. 50W) may instead be inserted
in series with the Storage Capacitor to limit the in-
rush current.

4.4 Linear Motor Current Control

The output current is controlled in a linear fashion
via a transconductance loop. Referring to Figure
4-4 the sourcing FET of one phase is forced into
full conduction by connecting the gate to V

pump

while the sinking transistor of an appropriate
phase operates as a transconductance element.
To understand the current control loop, it will be
assumed that Q2 in figure 4-4 is enabled via SW3
by the sequencer. During a run condition, the cur-
rent in Q2 is monitored by a resistor R

connected

to the R

sense

input.

The resulting voltage that appears across R

amplified by a factor of four by A3 and is sent to
A2 where it is compared to the Current Command
Signal. A2 provides sufficient drive to Q2 in order
to maintain the motor speed at the proper level as
commanded by the Speed Controller.

4.5 Transconductance Loop Stability
The RC network connected to the Compensation
pin provides for a single pole/zero compensation
scheme. The pole/zero compensation scheme.

The pole/zero locations are adjusted such that a
few dB of gain (typ. 20dB) remains in the tran-
sconductance loop at frequencies higher than the
zero.

The inductive characteristic of the load provides
the pole necessary for loop stability. Thus the
loop bandwidth is actually limited by the motor it-
self.
Figure 4-5 shows the complete transconductance
loop including compensation, plus the response.
The Bode plot depicts the normal way to achieve
stability in the loop. The pole andzero are used to
set a gain of 20dB at a higher frequency and the
pole of the motor cuts the gain to achieve stabil-
ity.
Loop instability may be caused by two factors:

1)The motor pole is too close to the zero. Refer-

ring to figure 4.6, the zero is not able to dec-
rement the shift of phase, and when the effect
of the pole is present, the phase shift may
reach 180

�

and the loop will oscillate. To rec-

tify this situation, the pole/zero must be
shifted at lower frequencies by increasing the
compensation capacitor.

Figure 4-5

Figure 4-6

Figure 4-7

L6238S

18/31

2)The motor capacitance, CM, itself can inter-

fere with the loop, creating double poles. If
the gain at higher frequencies is sufficiently
high, the double pole slope of 40dB/decade
can cause the phase shift to reach 180

�

re sulting in oscillation.

Figure 4-8 is a Bode plot showing how to correct
this situation. The bold line indicates the response
with relatively high gain at the higher frequencies.
By leaving the pole unchanged and increasing the
zero, the response indicated by the dashed lines
can be achieved.

4.6 Slew Rate Control
A 3-phase motor appears as an inductive load to
the power supply. The power supply sees a dis-

turbance when one motor phase turns OFF and
another turns ON because the FET turn-OFF time
is much shorter than the L/R rise time. Abrupt
FET turn-OFF without a proper snubbing circuit
can even cause current recirculation back into the
supply.
However, the need for a snubber circuit can be
eliminated by controlling the turn-OFF time of the
FETs.
The rate at which the upper and lower drivers turn
OFF is programmable via an external resistor,
S

slew

connected to the SLEW RATE pin. This re-

sistor defines an internal current source that is
utilized to limit the voltage slew rate at the outputs
during transition, thus minimizing the load change
that the power supply sees.
To insure proper operation the range of resistor
values indicated should not be exceeded and in
some applications values near the end points
should be avoided as discussed below.
Low Values of Rslew - If a relatively low value of
Rslew is selected, the resultant fast slew rate will
result in increased commutation cross-over cur-
rent, higher EMI, and large amount of commuta-
tion current.

This last case can cause voltage spikes at the
output that can go as much as lV below ground
level. This situation must be avoided in this inte-
grated circuit (as in most) since it causes unpre-
dictable operation.

High Values of Rslew - Higher values of Rslew
result of course in slow slew rates at the outputs
which is, under most conditions, the desired case
since the problems associated with fast rates are
reduced. The additional advantage is lower
acoustical noise.
Problems can occur though if the slew rate for a

Figure 4-8

Figure 4-9: Effect of Slow Slew Rate.

L6238S

19/31

given application is too slow. Figure 4-9 is an os-
cillograph taken on a device that had a fairly large
value for Rslew and failed to spin up and phase
lock a motor.
The problem manifests itself as the motor begins
to spin up. At lower RPMs, the Bemf of the motor
is relatively small resulting in higher amounts of
commutation current. In figure 4-9, the upper
waveform is the voltage appearing at OUTPUT
relative to the CENTER TAP input. The lower
waveform is the actual output of the Bemf ampli-
fier available on special engineering prototypes.
The oscillograph was taken just as the problem
occured. The period between zero crossings was
~800

�

s resulting in a mask time period of 200

�

As can be seen, the excessively long slew rate
actually exceeded the mask period and was de-
tected as a zero crossing.
This resulted in improper sequencing of the out-
puts relative to the proper phases and caused the
motor to spin down.

4.7 Ext PFET Driver
The power handling capabilities of the 3 phase
output stage can be extended with the addition of
a single P-Channel FET.

Figure 4-10 shows the Ext FET connection and
demonstrates how the L6238S automatically
senses the FETs presence. When the voltage at
the Gate Drive pin is

0.7V, the output of com-

parator A3 goes high, removing the variable drive
A1 from the internal FETs and connects them in-
stead to Vanalog via the commutation switches to
facilitate full conduction.

The upper FETs drive paths are not shown for
clarity. A3 also closes SW2 allowing A1 to linearly
drive the external P-Channel FET Q1 via inverter
A2.

4.8 Bemf Ampolifier
Since no Hall Effect Sensors are required, the
commutation information is derived from the Bemf
voltage zero-crossings of the undriven phase with
respect to the center tap. The Bemf comparator
and associated signal levels are depicted in figure
4-11. For reliable operation, the Bemf signal am-
plitude should be a minimum of

�

60 mV to be

properly detected. In order to provide for noise
immunity, internal hysteresis is incorporated in
the detection circuitry to prevent false zero cross-
ing detection.
For laboratory evaluation purposes, a simple re-

Figure 4-10: External P-Fet.

L6238S

20/31

sistive network as shown in figure 4.12 can be
used to emulate the Bemf of the motor.
The actual Bemf zero-crossing is 30 electrical de-
grees (50% of a commutation interval) away from
the optimal switch point. A digital counter circuit
measures 50% of the previous interval to deter-
mine the next interval's commutation delay from
the zero crossing. During the low RPM stages of
start up the long commutation intervals may
cause the counter to overflow, in which case 50%
of the max count will be less than 50% of the
ideal commutation interval. Therefore, the torque

will not be optimal until the desired commutation
interval is less than the dynamic range of the
counter.

4.9 Center Tap Protection
Spindle Motors with a high number of windings
exhibit a transformer coupling effect that in some
cases can cause relatively high currents to flow
through the center tap input.
Current flowing out of the center tap pin as high
as 25mA has been observed with certain motors.

Figure 4-12: Bemf Emulator

R1 1K

DS1

TO CENTER

TAP INPUT

D95IN317

Figure 4-13

Figure 4-11: Bemf Amplifier.

BEMF

-35

-25

BEMF(mV)

SLOPE=0

SLOPE=1

D95IN316

L6238S

21/31

The high current flows from the grounded sub-
strate of the integrated circuit (p-type material),
through one or more epitaxial pockets (n-type ma-
terial) and out the center par pin.

This current can cause adverse operation of the
controllet due to substrate injection and might
possibility damage the internal metalization runs.
The normal current for this input is in the 200

�

range.

Referring to figure 4-13, a simple protection
scheme consisting of a 1K resistor and a low cur-
rent Schottky diode should be added if the appli-
cation causes excessive current (i.e. >1mA) to
flow through the center tap pin.

5.0 PWM MOTOR CURRENT CONTROL
A unique feature of the L6238S in the optional
Pulse Width Modulation (PWM) control of motor
current.
Using Variable-frequency, Constant-OFF time
Current-Mode control, the L6238S can drive
higher power motors without the need for external
drivers, while minimizing internal power dissipa-
tion.
Additional benefits include reduced power supply
consumption (up to 50% savings) and lower watt-
age requirements for the current sensing resistor.
Constant-OFF time Current-Mode control, oper-
ates on the principle of monitoring the motor cur-
rent and comparison it to a reference or control
level.

When the motor current reaches this commanded
level, the output drivers turn OFF and remain
OFF for a Constant-OFF time. After this OFF time
the drivers turn back ON to repeat the cycle.
Figure 5.1 is a block diagram of the PWM control
circuitry. When using PWM as opposed to linear
control, two changes are made to the control
loop:

1.The slew rate control is disabled, allowing the

outputs to slew at a minimum rate of 10V/

�

This is accomplished by closing SW3 and
SW5.

2.The OTA amplifier is taken out of the control

loop via SW6. The lower drivers are now
driven into hard conduction by tying the gates
to the analog supply during the On time of the
PWM cycle.

The current in the motor windings is monitored via
the voltage dropped in the sensing resistor,
R

sense

This voltage is multiplied by a factor of 4 in the
Current Sense Amplifier (CSA) and sent to nega-
tive input of the PWM Comparator (A2).
The control voltage, V

control

, is applied to the posi-

tive input of A2. When the output of the CSA
reaches a level that is equal to the commanded
level, the output of A2 switches low, toggling the
latch comprised of N1 and N2. This causes the
upper drivers to turn off and opens SW1. Q3 turns
OFF allowing the Constant-OFF time capacitors,

Islew

PUMP

SW2

Cfet

UPPER A

PWM/SLEW

VPOWER

Islew

SW3

Cfet

OUTPUT

OUTA

SLEW RATE

REFERENCE

CURRENT

SLW

RSENSE

CSA

VCTRL

LOWER A

D95IN318

VANALOG

3.1V

SW1

1.2V

SW5

SW4

PWM/LIN

CONTROL

FROM TRANS. LOOP

CSA

SW6

ANALOG

COFF

RSLEW

Figure 5-1

L6238S

22/31

off

to discharge to dischargte through R

slew

, initi-

ating the Constant-OFF time-out. When the volt-
age on C

off

reaches 1.2V, comparator A1switches

state toggling the latch in the opposite state, turn-
ing the upper driver back ON. SW1 also closed
quickly charging up C

off

for the next cycle.

5.1 PWM Design Considerations
In order to select the parameters associated with
PWM operation, the following factors must be
taken into consideration:
1. PWM Switching Frequency

2. Duty Cycle
3. Motor Currents
4. Minimum ON Time
5. Noise Blanking
6. Bemf Masking/Sampling

5.1.1. PWM Switching Frequency
The PWM switching frequency F

pwm

is found

from:

pwm

off

(5.1.1)

where:

= The time required for the motor current

to reach the commanded level.

off

= The programmed OFF time.

The two main considerations for this parameter
are the minimum and maximum switching fre-
quency.
The maximum switching frequency occurs during
the Start-up and should be kept below 50KHz due
tointentional bandwidth limitations and output
switching losses.

5.1.2 Duty Cycle
Besides reducing the power dissipation of the
controller output stage, running in PWM offers 2
additional "free" benefits:

A. Reduced Powe Supply Current at Start Up

B. Lower Power Rating for the Motor Current

Sense Resistor.

Figure 5-2 is the current path during the ON time
of a phase period. The current from the supply
passes through the upper sourcing DMOS, Q3
transistor through the two driven winding, the
lower DMOS, Q2 and finally through the current
sensing resistor R

sns

. Since both Q3 and Q4 are

ON, while Q3 is turned OFF. The voltage, causing
the current to continue to flow through Q2, and
Q4.
If the duty cycle is nearor at 50%, then for 1/2 the
PWM cycle, no current is flowing from the power
supply or the sense resistor while current is still
flowing in the motor. This lowers the requirement

for both the Power Supply and the Power Rating
for the sensing resistor.

5.1.3 Motor Currents

Note: It is not the objective of this section to describe the principles
of brushless DC motor, but to provide sufficient information about the
parameters associated with PWM operation in order to optimize an
application.

A simplified model of a motor is shown in figure 5-
4. For this discussion, lower order effects due to
mutual inductance between windings, resistance
due to losses in the magnetic circuit, etc. are not
shown.
The motor at stall is equal to a resistance, Rmtr,
in series with an inductance, Lmtr. When the mo-
tor is rotating, there is an induced emf that ap-
pears across the armaure terminals and is shown
in figure 5-4 as an internally generated voltage
Ibemf), Eg.

OUTPUTA

OUTPUTB

POWER

SENSE

SNS

D95IN319

Figure 5-2

OUTPUTA

OUTPUTB

POWER

SENSE

SNS

D95IN320

Figure 5-3

L6238S

23/31

The relation between these variables is given by:

mtr

(5.1.2)

where:

Applied Voltage

mtr

Motor Current

mtr

Total

inductance

the

motor

windings

mtr

Resistance in series with the motor

The internally generated voltage of
the motor, proportional to the motor
velocity

Since:
E

= K

(5.1.3)

The above equations can be combined to form
the basic electrical equation for a motor:

mtr

(5.1.4)

Figure 5.5 is a simplified electrical equivalent of
the output stage of the L6238S along with the
model of the motor during the time that the Out-
put Drives are conducting.

The additional resistance associated with the out-
put stage and sensing resistor are also in series
with the motor. If we let R

equal the total series

resistence:

= 2*R

dsON

+ R

mtr

+ R

sense

(5.1.5)

then (5.1.4) becomes:

mtr

(5.1.6)

Figure 5-6 is an equivalent circuit of the output
stage during the Constant-OFF period. During the
OFF time the lower driver for the particular phase
beign driven remains ON.
The internally generated voltage forces the path
of current though the motor, its series resistance,
the RdsON of the Lower Driver and finally through
the opposite lower driver.

PWM Example (Refer to Figure 5-7)
The following is an example on how to select the
timing parameters.

Given:

DCStart Current

1.25A

Ripple Current

100mA

Duty Cycle

50%

Motor Interface (L)

880

�

Total Series Resistance (R

)

4.8

If the worst case start current is 1.25A and the
duty cycle is 50%, then the Peak Current, It will
be:
i

1.25

0.1

= 1.30A

Rmtr

Lmtr

D95IN321

Figure 5-4

Rmtr

Lmtr

D95IN322

UPPER

Rdson

KEW

LOWER

Rdson

Rsense

Figure 5-5

Rmtr

Lmtr

D95IN323

KEW

LOWER

Rdson

LOWER

Rdson

Figure 5-6

L6238S

24/31

The Valley current, I

will thereforebe:

= 1.30 - 0.1A

= 1.20A

During the Align and Go Phase (where the power
dissipation requirements are highest, Eg is zero.
The initial time required to reach the Peak current
is:

init

= �

�

I,R

(5.1.7)

Substituting values:

init

= �

880e

�

4.8

�

1.3

4.8

init

= 134.6

�

The ON time can be calculated from:

�

(5.1.8)

Substituting values:

880E

�

4.8

�

1.2

4.8

�

1.3

= 14.67

�

During the OFF time, the motor current continues
to flow through the DMOS transistors and threfore

the voltage drop remains constant across the
windings.
The time required for the inductor current to reach
the valley current is given by:

off

(5.1.9)

Substituting values:

off

880e

�

4.8

1.3
1.2

off

= 14.67

�

Note: that the parameters for this example were selected to arrive at
a 50% duty cycle. This will not always be the case due to factors such
as fixed motor parameters, etc.

The Constant Off timer period can be determined
from:

off

slew

off

chrg

trip

(5.1.10)

Where:

off

Constant-OFF Time

slew

Slew Rate Resistor

off

Off Time Capacitor

chrg

Initial Capacitor Charge Voltage

trip

Capacitor Lower Trip Threshold

Substituting nominal values given:

off

= 0.75

slew

off

Solving for C

off

0.75R

slew

In the example, to set the OFF timer for a 50%
duty cycle:

Given:

off

14.67

�

slew

100K

(typical Value)

off

14.67e

�

100e

off

146pF

5.1.4 Minimum ON Time
The bandwidth of the PWM loop was optimized to
reject unwanted switching noise while providing

�

s/DIV

Iout A

200mA

D95IN324

It=1.3A

Ib=1.2A

Iavg=1.25A

Figure 5-7

L6238S

25/31

sufficient response, commensurate with

the

switching speed of the output drivers. At higher
frequencies the switching losses inherent in the
drivers start to negative any of the power dissipa-
tion savings gained with PWM operation.
The current sense amplifier has a minimum slew
rate of 0.31V/

�

s. With a worst case Motor peak

start-up current of 2.5A and Sense Resistor of
0.33, the resultant R

sense

voltage would be equal

to 825mV. With a minimum gain of 3.8V/V, the
CSA output voltage would have to slew to 3.14V.
Therefore it would require approximately 10

�

s for

the output voltage to reach the required com-
manded level.
If an ON time were selected that was less than
this time, the motor current would overshoot the
desired level resulting in incorrect current control
possibly exceeding the output capabilities of the
drivers.

5.1.5 Noise Blanking

Referring to Figure 5-8, when operating with
lower levels of current (i.e. < 700mA, with Rsense
= 0.33

), the possibility exiss where the noise

due to output Turn-ON can exceed the Com-
manded Current Level causing prematire Turn-
OFF.
In order to provide noise immunity from this
switching noise, a blanking circuit automatically
rejects any signal appearing at the output of the
CSA for a 3

�

s period.

Figure 5-9 is an additional block diagram of the
PWM control loop including the noise blanking cir-
cuit. The output of A3 goes high when ever the
voltage at the CSA input is more positive then the
Control Voltage.
This is the case when either the motor current or
the turn-ON transient has reached the com-
manded level. The output of A3 is gates by N11.
In order to provide a blanking period, Q1 is turned

�

s/DIV

Vrsense

D95IN325

�

s BLANKING PULSE

COMMANDED

CURRENT LEVEL

Figure 5-8

8pF

N10

�

DELAY

TO OUPUT

DRIVERS

N11

N12

2.4V

SW1

1.2V

CLK_BEMF

�

PWM/LIN

RUN/BRAKE

N12

PWM TIMER

PWM COMP

VCONTROL

CSA INPUT

PWM_SLEW

D95IN326

Figure 5-9

L6238S

26/31

ON during the Constant-OFF time, charging C1 to
the internal rail. At the end of the OFF time, Q1 is
turned OFF allowing current source I1 to dis-
charge the capacitor towards ground. While the
voltage on C1 is above the low input threshold of
N1, the output of N1 is low, preventing any
change of state at the output of N11 due to a high
A3 output. When the capacitor reaches the low in-
put threshold of N1, N1 chnges state allowing A3
to control the state of N11.

5.1.6 Masking/Bemf Sampling in PWM
The method of sampling the floating phase for the
bemf zero crossing defers between Linear and
PWM operation. In Linear Mode, the bemf is sam-
pled continuously after the mask time-out, until
the zero crossing is detected. Then the mask is
enabled for a time based on the commutation
phase delay plus the additional time based on the
previous period as explained earlier.
With PWM operation however, the switching
noise at turn ON (after the Constant-OFF time)
can be significant, especially at low RPMs where
the bemf is the lowest. In order to provide the
greatest noise immunity in PWM, the floating
phase is monitored only at the point where the
output is about to be turned OFF.
In operation, when the motor current reaches the
commanded level, the floating phase is first moni-
tored to determine if the bemf has crossed the
zero. The output is then turned OFF for the Con-
stant-OFF time out.
As the motor current increases through, the in-
creasing bemf causes the motor current to natu-
rally decrease. Eventually a point is reached
where the PWM is running at 100% duty cycle
and the motor current cannot reach the com-
manded level. At this time the bemf is no longer

smpled, preventing further commutation of the
output.
The PWM Limit Timer is used to set up a maxi-
mum ON time. When this limit is exceeded the
method of sensing the bemf is essentially the
same as in the case of operating in linear mode.

Figure 5-10 is an oscillograph of the controller op-
erating in PWM mode. The top trace is A

out

. The

2nd trace is the voltage seen at the PWM/SLEW
pin indicating the exponential discharging of the
timing capacitor during the OFF time. Trace 3 is
the voltage appearing on the PWM Timer capaci-
tor, while trace 4 is the motor current.
Referring again to Figure 5-9, and 5-10 transistor
Q2 is turned ON at the beginning of the OFF time,
discharging the external capacitor C4 to near
ground level. At the end of the OFF-Time, Q2 is
turned off and C4 starts charging linearly via I2.
C4 is again discharged at the beginning of the
OFF time and the cycle repeats. As long as C4
does not reach the threshold of A1 (typically
3.5V), the bemf is only sampled just before turn-
off of the output. As the motor is starting up in fig-
ure 5-10, the duty cycle is roughly 50%. The
PWM limit timer is reset to ground by the start of
the OFF timer before reaching the 3.5V threshold.
In figure 5-11, as the motor spins up, the on time
of the output increases and the PWM limit timer
reaches the 3.5V. Eventually the duty cycle
reaches 100% and the sampling of the bemf is
essentially the same as in the linear mode.
The selection of components for the PWM timer is
not critical. Since the objective is to sample the
bemf only at turn OFF to maximize the signal to
noise ratio, the PWM timer slope can be set up to
convert to the full bemf sampling after a few revo-
lutions of the motor when the bemf has reached
an appropriate voltage output.

�

s/DIV

Iout A

Aout

D95IN327

Fpwm=50KHz
Coff=120pF
Ctmr=220pF

500mV

PWM/Slew

10v

PWM Limit

Timer

Figure 5-10

�

s/DIV

Aout

Iout A

D95IN328

Fpwm=12KHz
Coff=120pF
Ctmr=220pF

500mV

PWM/Slew

10V

PWM Limit

Timer

Figure 5-11

L6238S

27/31

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

�

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Электронный компонент: L6238S