GENERAL

5V (+/- 10%) OPERATION.
REGISTER BASED ARCHITECTURE
MINIMUM EXTERNAL COMPONENTS
BICMOS + VERTICAL DMOS (1.5mm)

VCM DRIVER

1.5A DRIVE CAPABILITY
0.9

TOTAL BRIDGE IMPEDANCE AT 25

LINEAR MODE
PHASE SHIFT MODULATION (PWM MODE)
INSTANTANEOUS, (GLICH FREE) SWITCH

BETWEEN THE 2 MODES

CLASS AB OUTPUT DRIVERS
ZERO CROSSOVER DISTORSION
14 BIT DAC DEFINE OUTPUT CURRENT
SELECTABLE TRANSCONDUCTANCE
4 PROGRAMMABLE PARKING VOLTAGE
DYNAMIC BRAKE

SPINDLE DRIVER

2.0A DRIVE CAPABILITY
0.8

TOTAL BRIDGE IMPEDANCE AT 25

BEMF, INTERNAL OR EXTERNAL, PROC-

ESSING

SENSOR-LESS MOTOR COMMUTATION
PROGRAMMABLE COMMUTATION PHASE

DELAY

LINEAR MODE AND CONSTANT TOFF PWM

OPERATION MODE

INTERNAL FREQUENCY LOCKED LOOP

SPEED CONTROL (FLL)

BEMF RECTIFICATION DURING RETRACT
BUILT-IN ALIGNAMENT&GO START-UP
INDUCTIVE SENSING START UP OPTION
RESYNCHRONIZATION
DYNAMIC & REVERSE BRAKE
CONTROLLABLE OUTPUT SLEW RATE

OTHER FUNCTIONS

5V MONITORING WITH EXTERNAL SET

TRIP POINTS AND HYSTERESIS

POWER UP/DOWN SEQUENCING
LOW VOLTAGE SENSE

3.3V INPUT LOGIC COMPATIBILITY
THERMAL SHUTDOWN AND PRETHERMAL
WARNING
SYSTEM CLOCK WATCHDOG

DESCRIPTION

The L6275 integrates into a single chip both spin-
dle and VCM controllers as well as power stages.
The device is designed for 12V disk drive applica-
tion requiring up to 2.0A of spindle and 1.5A of
VCM peak currents.

A serial port with up to 25 MHz capability provides
easy interface to the microprocessor. A register
controlled Frequency Locked Loop (FLL) allows
flexibility in setting the spindle speed. Integrated
BEMF processing, digital masking, digital delay,
and sequencing minimize the number of external
components required.
Power On Reset (POR) circuitry is included. Upon
detection of a low voltage condition, POR is as-
serted, the internal registers are reset, and spin-
dle power circuitry is tri-stated. The BEMF is recti-
fied providing power for actuator retraction
followed by dynamic spindle braking.
The device is built in BICMOS technology allow-
ing dense digital/analog circuitry to be combined
with a high power DMOS output stage.

This is preliminary information on a new product now in development. Details are subject to change without notice.

April 1999

TQFP44 (10x10mm)

ORDERING NUMBER: L6275

L6275

5V DISK DRIVE SPINDLE & VCM, POWER

& CONTROL "COMBO"

PRODUCT PREVIEW

BICMOS TECHNOLOGY

1/17

CHARGE

PUMP

ISO

DRIVER

SUPPLY &

CLOCK FAULT

MONITORS

FREQUENCY

LOCK LOOP

SPINDLE SEQUENCER

REFERENCE

VOLTAGE

GENERATOR

14 BIT

VCM DAC

ZERO CROSS

DETECTION

A+

A-

A=4

SUPPLY

FLL_RES

FLL_FILTER

SYS_CLK

FCOM

SPN_COMP

BRK_CAP

PWM/SLEW

VDD

POR_DELAY

PORB

VDD

GND

DGND

V5/2

VCM_CAL

ERROR_IN

ERROR_OUT

SENSE_OUT

OUT_A

OUT_B

RSENSE

OUT_C

VCM_A+

VDD

VCM_A-

SENSE_IN-

SENSE_IN+

D99IN1050

VCM_GND

CTAP

SW1

SDATA

SCLK

SDEN

CLK_MON

TR_5V

ISENSE

INDEX

THERMAL

DAC

VCM

CALIBRATION

BEMF

RECTIFICATION

PARKING

VCM CURRENT

CONTROL PSM/LIN

START-UP

RE_SYNC

DYNAMIC/
REVERSE

BRAKE

SPINDLE

CURRENT
CONTROL

PWM/LIN

BEMF

PROCESSING

SERIAL

INTERFACE

REGISTERS

BLOCK DIAGRAM

R_SENSE

I_SENSE

OUT_C

CTAP

FCOM

PWM/SLEW

INDEX

OUT_A

R_SENSE

OUT_B

GND

BRK_CAP

VDD

DGND

SYS_CLK

SDATA

SDEN

SCLK

VDD

V5/2

FLL_FILTER

VCM_CAL

SPN_COMP

VDD

AGND

DAC

ERROR_IN

CLK_MON

ERROR_OUT

SENSE_OUT

POR_DELAY

TR_5V

PORB

VCM_GND

SENSE_IN+

VCM_A-

VDD

SW1

FLL_RES

VDD

SENSE_IN-

VCM_A+

D99IN1051

PIN CONNECTION

L6275

2/17

PIN DESCRIPTION (Pin Types: D = Digital, P = Power, A = Analog)

Name

Function

FCOM

Output of the Spindle zero cross or Current Sense circuit.

CTAP

Spindle Central Tap used for differential BEMF sensing.

PWM/SLEW

RC network sets the Spindle Linear Slew Rate and PWM OFF-Tim e.

OUT_C

Spindle DMOS Half Bridge Output and Input C for BEMF sensing.

I_SENSE

Input to sense the voltage the SPINDLE Sense Resistor.

R_SENSE

Output connection for the Motor Current Sense Resistor to ground.

OUT_B

Spindle DMOS Half Bridge Output and Input B for BEMF sensing.

GND

Spindle Ground (Substrate).

R_SENSE

Output connection for the Motor Current Sense Resistor to ground.

OUT_A

Spindle DMOS Half Bridge Output and Input A for BEMF sensing.

INDEX

Input to allow Spindle to be locked to Index (servo) pulse.

BRK_CAP

Storage Capacitor for brake circuit. typically 5.9V.

VDD

+5V Power Supply for Spindle Power section.

DGND

Digital Ground.

SYS_CLK

Clock Frequency for system timers and counters.

SDEN

Serial Data Enable. Active high input pin for the serial port enable.

SDATA

Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8
bits of data. Open pin is at logic low as an input.

SCLK

Serial Port Data Clock. Positive edge triggered clock input for the serial data.

VDD

Digital/Analog power supply. +5V nominally.

V12/2

Reference Output for VCM control loop. Typically, half of the VCC except when parking.

FLL_FILTER

Speed loop R/C compensation connection used for FLL mode operation.

VCM_CAL

VCM loop offset voltage used for calibration.

External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V

External Charge Pump Capacitor.

VDD

+5V Power Supply for VCM Power section.

VCM_A-

VCM Power Amplifier negative output terminal.

SENSE_IN+

Non inverting Input of the Sense Amplifier for VCM block.

VCM_GND

Ground for VCM Power section.

SENSE_IN-

Inverting Input of the Sense Amplifier for VCM block.

VCM_A+

VCM Power Amplifier positive output terminal.

VDD

+5V Power Supply for VCM Power section.

FLL_RES

Resistor for setting accurate bias current sources for the chip (62K required).

SW1

External ISOFET driver.

PORB

Power on Reset Output. Low signal indicates the failure of the supplies.

TR_5V

Set Point Input for 5V Supply Monitor ( 2V threshold, 100mV Hysteresis)

POR_DELAY

Capacitor connection to set the Power on Reset Delay (3V threshold, 2

A charging)

SENSE_OUT

Output of the Sense Amplifier.

ERROR_OUT

Output of the Error Amplifier.

ERROR_IN

Inverting Input of the Error Amplifier.

CLK_MON

Watchdog clock monitoring pin

DAC

Output of the VCM DAC.

AGND

Analog Ground. For bang gap voltage reference.

VCC

+12V Power Supply for Spindle Power section.

SPN_COMP

External RC network that defines the compensation of the Spindle Transconductance Loop
in Linear Mode.

L6275

3/17

ELECTRICAL CHARACTERISTICS (All specifications are for 0 < T

amb

< 70

C, V

= 12V; V

= 5V,

FLL_RES = 62k

, unless otherwise specified.)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

POWER SUPPLIES

rectified

Supply Rectified

3.5

13.2

5V supply

4.5

5.5

Vdd

5V supply

SPINDLE + VCM

SPINDLE ONLY

VCM ONLY

THERMAL SENSING

Shutdown Temperature

150

180

HYS

Hysteresis

Early Warning

-25

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

Maximum Supply voltage

-0.5 to 14

Maximum Logic supply

-0.5 to 6

in max

Maximum digital input voltage

+0.3V

in min

Minimum digital input voltage

GND - 0.3V

SPINDLE I

peak

Spindle peak sink/source output current

2.1

VCM I

peak

VCM peak sink/source output current

1.6

tot

(*)

Maximum Total Power Dissipation

1.7

stg

, T

Maximum Storage/Junction Temperature

-40 to 150

THERMAL DATA

Symbol

Parameter

Value

Unit

th j-case

Thermal Resistance Junction to Case

C/W

th j-amb

(*)

Thermal Resistance to Junction to ambient

C/W

(*) In typical application with multilayer 120X120mm Printed Circuit Board

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Value

Unit

Supply Voltage

4.5 to 5.5

amb

Operating Ambient Temperature

0 to 70

Junction Temperature

0 to 125

L6275

4/17

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY MONITOR

Trip Point

Input Rising

1.92

2.08

HYS

Hysteresis Voltage

Input falling

100

DLY

Porb Delay Current

TR_5V, TR_12V > V

Vpordly = 2V

1.5

2.5

on_por

Porb Pull Down Ron

> 2V and sink 1mA

pordly

= 2V

500

DLY

Porb Dly Threshold

TR_5V > V

2.0

Input Current

< 4V

-1

VOLTAGE BOOST

BOOST

Output Voltage

+6.3

osc

Internal Oscillator

130

200

250

kHz

SYSTEM CLOCK WATCHDOG

Min_Clk

Min. System Clock Time

SW1 OUTPUT

GATE

Gate Driver for External Mosfet

Internal Resistor to CP

200

GATE

Off Gate State Voltage for
External Mosfet

= 1mA V

= 3.5V

0.7

DIGITAL LOGIC LEVELS

Input Logic "1"

2.5

Input Logic "0"

0.5

Output Logic "1"

SOURCE

= 20

-0.2

Output Logic "0"

SOURCE

= -400

0.4

SYSCLK

System Clock

MHz

VCM, DAC

Resolution

Bits

Differential Linearity

1 LSB Change
- Tested
- By design

-1

-0.5

0.5

LSB

Integral Linearity

Bits

Midscale Offset

Referenced to V

-5

Convertion Time

Full Scale Voltage

Referenced to V

Full Scale Error

-4

VCM, ERROR AMPLIFIER

VOL

Open Loop Gain

Input Offset Voltage

-5

Input Bias Current

--250

250

ICM

Input Common Mode Range

/2-

0.5

/2+

0.5

ELECTRICAL CHARACTERISTICS (Continued)

L6275

5/17

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Vclamp

Output Clamp Voltage

-1mA < I

< 1mA

Lowside/Highside clamp

1.4V

ODB

Unity Gain Bandwidth

MHz

VCM, POWER STAGE

DS(ON)

Output ON Resistance (Each
device)

= 25

= 125

0.5
0.8

Operating Current

1.3

O(LEAK)

Output Leakage Current

= 5.5V

1.0

VCM, CURRENT SENSE AMPLIFIER

Voltage Gain

3.88

4.12

V/V

ICM

Input Common Mode Range

-0.3

+0.3

OCM

Output Common Mode Range

-3mA < I

< 3mA

-2

Output Offset Voltage

SENSE_IN (

) = V

-15

3dB

3dB Bandwidth

MHz

CMRR

Input Common Mode Rejection

PSRR

Power Supply Rejection Ratio

VCM, RETRACT

park

RETRACT VOLTAGE

PKV_1 = 0 & PKV_2 = 0
PKV_1 = 0 & PKV_2 = 1
PKV_1 = 1 & PKV_2 = 0
PKV_1 = 1 & PKV_2 = 1

0.850
0.650
1.600
1.150

mV
mV
mV
mV

Tretract

Retract Time
limited by the internal oscillator
200kHz

RT0 = 0 & RT1 = 0
RT0 = 0 & RT1 = 1
RT0 = 1 & RT1 = 0
RT0 = 1 & RT1 = 1

160
320

160

ms
ms
ms
ms

SPINDLE, PWM CURRENT SENSE COMPARATOR

DLY

Delay to FCOM Out

200

500

SPINDLE, POWER STAGE

DS(ON)

Output On Resistance (Each
device)

= 25

= 125

0.45
0.74

Start-Up Current

O(LEAK)

Output Leakage Current

VCC = 14V

1.0

Output Slew Rate (Linear)

slew

= 100k

0.2

0.3

0.5

Output Slew Rate (PWM)

Reg#8Eh, Bit 0 = 0
Reg#8Eh, Bit 0 = 1

10
20

BEMF

MIN

Minimum BENF Voltage for
Detection

mVp-p

HYS

Hysteresis

FLL CHARGE PUMP OUTPUT

LEAK

Off State Leakage

0 < Vfll_res , 3V

-50

+50

On State Current

FLL_RES = 62k

ICP = "1"
ICP = "0"

22
80

100

120

RCP

Current Set Voltage

FLL_RES = 62k

1.18

1.225

1.25

ELECTRICAL CHARACTERISTICS (Continued)

L6275

6/17

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

CURRENT SENSE AMPLIFIER

BIAS

Input Bias Current

Voltage Gain

3.8

4.0

4.2

V/V

Output Slew Rate

SERIAL PORT

Symbol

Parameter

Min.

Typ.

Max.

Unit

SCK

SCLK Period

CKL

SCLK low time

CKH

SCLK high time

SDENS

Enable to SCLK

SDENH

SCLK to disable

Data set-up time before rising edge SCLK

Data Hold Time

SDENL

Minimum SDEN Low Time

SDV

SCLK falling edge (A6) to SDATA valid on READ op.

SDV

SCLK rising edge (D0-D7) to SDATA Transition on READ op.

ELECTRICAL CHARACTERISTICS (Continued)

1st Byte

2nd Byte

SDEN

SCLK

SDATA

SERIAL PORT WRITE TIMING

SERIAL PORT READ TIMING

1st Byte

2nd Byte

D98IN844

SDEN

SCLK

SDATA

Figure 1. Serial Port Timing Information.

L6275

7/17

SERIAL PORT OPERATION
The serial port interface is a bi-directional port for reading and writing programming data from/to the in-
ternal registers of this device. For data transfers SDEN* is brought high, serial data is presented at the
SDATA pin, and a serial clock is applied to the SCLK pin. After the SDEN* goes high , the first 16 pulses
applied to the SCLK pin will shift the data presented at the SDATA pin into an internal shift register on
the rising edge of each clock. An internal counter prevents more than 16 bits from being shifted into the
register. The data in the shift register is latched after the 16th SCLK pulse. If less than 16 clock pulses
are provided before SDEN* goes low, the data transfer is aborted.
All transfers are shifted into the serial port LSB first. The first byte of the transfer is for R/W and address
and instruction information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ.
Following 7 bits are Address.

INSTRUCTION, 1 BIT

ADDRESS, 7 BITS

D98IN845

DATA, 8 BITS

SDEN

SCLK

SDATA

Figure 2. Serial Port Data Transfer Format.

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

0
VCM DAC (High) Register
Write only
0Eh

BIT

LABEL

DESCRIPTION

VDAC BIT8

VCM DAC bit 8

VDAC BIT9

VCM DAC bit 9

VDAC BIT10

VCM DAC bit 10

VDAC BIT11

VCM DAC bit 11

VDAC BIT12

VCM DAC bit 12

VDAC BIT13

MSB resistor ladder of the 14 bit VCM DAC

PSM/LINEAR

Selects Voice Coil PSM or Linear Output Current Control. 1=PSM
0=Linear.

VCM_CAL

VCM calibration. 1 = Enables VCM control circuits and tristates
VCM power transistors.

L6275

8/17

INTERNAL REGISTER DEFINITION
VCM DAC (High and Low) Registers
Bit 0 through 5 of the VCM DAC (High) Registers and bit 0 through 7 of the VCM DAC (Low) Registers
control the absolute value of the voice coil current. Bit is the sign bit, controlling the current direction. All
the 13 bits are part of a resistor divider network.

Note. It is required to write on register 1 to make effective changes on register 0.

Reg:
Name:
Type:
Address:

1
VCM DAC (Low) Registers
Write only
1Eh

BIT

LABEL

DESCRIPTION

VDAC BIT0

LSB resistor ladder of the 14 bit VCM DAC

VDAC BIT1

VCM DAC bit 1

VDAC BIT2

VCM DAC bit2

VDAC BIT3

VCM DAC bit3

VDAC BIT4

VCM DAC bit4

VDAC BIT5

VCM DAC bit5

VDAC BIT6

VCM DAC bit6

VDAC BIT7

VCM DAC bit7

Reg:
Name:
Type:
Address:

2
Spindle Control Register
Write only
2Eh

BIT

LABEL

DESCRIPTION

INCRE_SEQ

A 0 to 1 transition of this bit increments the spindle Sequencer.

START_UP

1 = Spindle Internal start up, 0 = Spindle External start up

R_SEQ

Reset Spindle sequencer. 1 = Reset sequencer to phase 1.

RUN

1 = Start Spindle ALIGN & GO, 0 = Reset Spindle control logic.

SPIN_EN

Enable Spindle section. 1 = Enable, 0 = Disable.

MEC/ELEC

Specifies electrical or mechanical cycle for Spindle FLL control.
1=Electrical, 0 = Mechanical.

PWM/LINEAR

Selects Spindle PWM or Linear Output Current Control. 1 = PWM,
0=Linear.

EXT/INT

External or internal Spindle loop feedback. 1 = external feedback
via index pin.

L6275

9/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

3
Spindle Delay Register
Write only
3Eh

BIT

LABEL

DESCRIPTION

MASK_TIME

Spindle BEMF Mask Time. 0 = 15 degree, 1 = 7.5 degree

MIN2

Control Spindle PWM on time

Min 1

Min2

Min. on Time

5.9

MIN1

1.4

5.21

8_12_POLE

Selects 8 or 12 pole motors. 1 = 8 pole, 0 = 12 pole.

SD3

Spindle commutation delay MSB

SD2

Spindle commutation delay bit

SD1

Spindle commutation delay bit

SD0

Spindle commutation delay LSB

SPINDLE PHASE DELAY
SD3-0 set the phase delay from BEMF zero crossing to the next commutation. The 30 theoretical degree
value can be changed to compensate for switching and other delays that are always present. The delay
adjustment range is from 1.875 through to 30 electrical degrees in 1.875 degree increments.

Reg:
Name:
Type:
Address:

4
FLL Coarse Counter Register
Write only
4Eh

BIT

LABEL

DESCRIPTION

Bit 4 of Spindle FLL Coarse Counter

Bit 5 of Spindle FLL Coarse Counter

Bit 6 of Spindle FLL Coarse Counter

Bit 7 of Spindle FLL Coarse Counter

Bit 8 of Spindle FLL Coarse Counter

Bit 9 of Spindle FLL Coarse Counter

C10

Bit 10 of Spindle FLL Coarse Counter

C11

MSB of Spindle FLL Coarse Counter

L6275

10/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

5
FLL Coarse/Fine Counter Register
Write only
5Eh

BIT

LABEL

DESCRIPTION

Bit 8 of Spindle FLL Fine Counter

Bit 9 of Spindle FLL Fine Counter

F10

MSB of Spindle FLL Fine Counter

Unused. Set = 0

LSB of Spindle FLL Coarse Counter

Bit 1 of Spindle FLL Coarse Counter

Bit 2 of Spindle FLL Coarse Counter

Bit 3 of Spindle FLL Coarse Counter

Reg:
Name:
Type:
Address:

6
FLL Fine Counter Register
Write only
6Eh

BIT

LABEL

DESCRIPTION

LSB of Spindle FLL Fine Counter

Bit 1 of Spindle FLL Fine Counter

Bit 2 of Spindle FLL Fine Counter

Bit 3 of Spindle FLL Fine Counter

Bit 4 of Spindle FLL Fine Counter

Bit 5 of Spindle FLL Fine Counter

Bit 6 of Spindle FLL Fine Counter

Bit 7 of Spindle FLL Fine Counter

L6275

11/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

7
Spindle Status Register
Read only
7Eh

BIT

LABEL

DESCRIPTION

THERMAL

Thermal Shutdown = 0 indicates that the chip temperature has exceeded 160

The bit will reset (=1) when the temperature falls below 130

C. When Thermal

Shutdown =0, the spindle logic will tristate both high and low side drivers,
protecting the output circuitry.

THERM_WARN

Thermal Shutdown Warning =0 indicates that the chip temperature is
approximately 25

C before the device goes in thermal shut down.

ROTOR_STUCK

0 = A sequential Spindle BEMF has not been detected

FAULT

1 = Rapid deceleration of the Spindle motor or High frequency on FCOM signal.

MASK_TIME

Mask Time toggled to "0" indicates that the Spindle BEMF is masked.

ERROR_LOCK

0 = Indicates error Spindle speed > 16msec/sample, either electrical or
mechanical.

ALIGN

0 indicate that the Spindle is in the Internal Start-Up Align Phase.

0 indicate that the Spindle is in the Internal Start-Up Go Phase.

Reg:
Name:
Type:
Address:

8
Spindle FLL Register
Write only
8Eh

BIT

LABEL

DESCRIPTION

SSLEW

Spindle PWM (chopping) Slew Rate. 0 = 10V

S, 1 = 20V

ICP

Spindle FLL Charge pump current. 1= 25

A, 0 = 100

Unused. Set = 0.

ISNS

1 = Puts output of the Spindle sense amplifier on FCOM pin and changes limit to
roughly 1/3 of normal.

IL1

Adjust maximum voltage on Spindle Rsense

IL0

Adjust maximum voltage on Spindle Rsense

CPL

1 = Spindle FLL Charge pump low

CPH

1 = Spindle FLL Charge pump high

"IL0"

"IL1"

"ISNS"

V(I_SENSE) LIMIT (

10%)

0.45V

0.50V

0.55V

0.75V

0.15V

0.20V

0.25V

0.30V

L6275

12/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

9
System Control Register
Write only
9Eh

BIT

LABEL

DESCRIPTION

PKV_1

VCM Parking Voltage

PKV_2

VCM Parking Voltage

1 = connects internal VR reference (2V) to level shift Opamp (for
Vcm calibration).

RT0 (*)

VCM Retract Time

DOUBLE

1 = Spindle Internal Start-Up Align and Energization time doubled.

VCM_EN

Enable VCM section. 1 = Enable, 0 = Disable.

RT1 (*)

VCM Retract Time

RETRACT

1= VCM retract

"PKV_1"

"PKV_2"

"PARKING VOLTAGE"

0.850V

0.650V

1.600V

1.150V

"RT0"

"RT1"

"RETRACT TIME"

160ms

320ms

80ms

160ms

(*) When program Retract Time (RT0 and RT1), Bit 2 REG#8Eh must be always written to 0.

L6275

13/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

10
Test Control Register
Write only
AEh

BIT

LABEL

DESCRIPTION

Unused. Set = 0

FLL_OUT

1 = Spindle Mech/Elec (see bit 5 register 2) output, 0 = Spindle
zero crossing output.

REV_BRAKE

Spindle Reverse Brake command. 1 = Brake. "0" has to be
reinserted to enable the spindle start up.

Unused. Set = 0

VB/DIS

1 = Disable Vboost

Reg:
Name:
Type:
Address:

11
VCM Control Register
Write only
BEh

BIT

LABEL

DESCRIPTION

VCMS

VCM PSM (chopping) Slew Rate. 0 = 10V/

s, 1 = 20V/

VCMH

1 = Forces VCM outputs to be High in PSM mode.

SLEEP

Unused (for future power saving mode).

COMSLEW

Spindle PWM (phase commutation) Slew Rate. 0 = 30V

s, 1 =

Unused. Set = 0

1 = Tristate the VCM outputs for half of the Retract Time during
retract.

1 = Brakes the VCM outputs for half of the Retract Time during
retract.

Unused. Set = 0

L6275

14/17

INTERNAL REGISTER DEFINITION

Reg:
Name:
Type:
Address:

12
Chip ID Register
Read only
FFh

BIT

LABEL

DESCRIPTION

ID_REV_0

Minor Revision Bit 0.

ID_REV_1

Minor Revision Bit 1.

ID_REV_2

Minor Revision Bit 2.

ID_REV_3

Minor Revision Bit 3.

ID_REV_4

Minor Revision Bit 0.

ID_REV_5

Minor Revision Bit 1.

ID_REV_6

Minor Revision Bit 2.

ID_REV_7

Minor Revision Bit 3.

1N4148

STN4NE03

VCC

5V_VDD

PORB

5V_VDD

12V_VCC

5V_VDD

2N2222

100nF

2.2

100nF

16V

(1)

16V

(1)

100nF

1nF

16V

(1)

20K

15K

10K

62K

10K

18.2K

220pF(3)

10nF(4)

51K

5K(4)

0.3(1W)

0.25(1W)

62K

620K

4.7K

5K(4)

13,43

6,9

VCC

RSENSE

ISENSE

CTAP

OUT_A

OUT_B

OUT_C

VCM_GND

OUT_C

VCM_A-

SENSE_IN+

VCM_A+

VCM_A-

25,31

SENSE_IN-

FLL-FILTER

FLL_RES

VCC

INDEX

VCM_A+

INDEX

SW1

POR_DELAY

BRK_CAP

PWM/SLEW

SPN_COMP

AGND

CLK_MON

GND

VDD

TR_5V

DGND

VCM_CAL

V12/2

DAC

ERROR_IN

ERROR_OUT

SENSE_OUT

SYS_CLK

SCLK

SDATA

SDEN

D99IN1052

FCOM

PORB

Voice Coil Ground

Power Ground

Analog Ground

(1) This capacitor must be Tantalum
(2) Place these components close to thedevice
(3) Do not mount this component if Spindle Linear mode is used
(4) Do not mount this component if Spindle Pwm mode is used

Digital Ground

Figure 3. Application Circuit.

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TQFP44 (10 x 10)

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.40

1.45

0.053

0.055

0.057

0.30

0.37

0.45

0.012

0.014

0.018

0.09

0.20

0.004

0.008

12.00

0.472

10.00

0.394

8.00

0.315

0.80

0.031

12.00

0.472

10.00

0.394

8.00

0.315

0.45

0.60

0.75

0.018

0.024

0.030

1.00

0.039

0°

(min.), 3.5

(typ.), 7

(max.)

Seating Plane

TQFP4410

0.10mm

.004

OUTLINE AND

MECHANICAL DATA

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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