1/16
L6598
February 2000
s
HIGH VOLTAGE RAIL UP TO 600V
s
dV/dt IMMUNITY
50V/ns IN FULL
TEMPERATURE RANGE
s
DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
s
SWITCHING TIMES 80/40ns RISE/FALL WITH
1nF LOAD
s
CMOS SHUT DOWN INPUT
s
UNDER VOLTAGE LOCK OUT
s
SOFT START FREQUENCY SHIFTING
TIMING
s
SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PROTECTION FEATURES
s
HIGH ACCURACY CURRENT CONTROLLED
OSCILLATOR
s
INTEGRATED BOOTSTRAP DIODE
s
CLAMPING ON Vs
s
SO16, DIP16 PACKAGES
DESCRIPTION
The L6598 is manufactured with the BCD OFF LINE
technology, able to ensure voltage ratings up to
600V, making it perfectly suited for AC/DC Adapters
and wherever a Resonant Topology can be benefi-
cial. The device is intended to drive two Power MOS,
in the classical Half Bridge Topology. A dedicated
Timing Section allows the designer to set Soft Start
Time, Soft Start and Minimum Frequency. An Error
Amplifier, together with the two Enable inputs, are
made available. In addition, the integrated Bootstrap
Diode and the Zener Clamping on low voltage sup-
ply, reduces to a minimum the external parts needed
in the applications.
DIP16
SO16N
ORDERING NUMBERS:
L6598
L6598D
HIGH VOLTAGE RESONANT CONTROLLER
BLOCK DIAGRAM
GND
V
REF
Ifmin
Rfmin
VCO
EN1
Vthe1
Vthe2
EN2
V
S
V
BOOT
OUT
C
BOOT
LOAD
H.V.
LVG
UV
DETECTION
Vs
HVG
BOOTSTRAP
DRIVER
HVG
DRIVER
LVG DRIVER
Css
V
REF
Ifstart
Rfstart
Cf
OP AMP
+
-
OPOUT
OPIN-
OPIN+
DEAD
TIME
DRIVING
LOGIC
CONTROL
LOGIC
Iss
+
-
+
-
LEVEL
SHIFTER
D98IN887A
12
5
6
7
4
2
3
1
9
8
10
11
14
15
16
L6598
2/16
PIN CONNECTION
THERMAL DATA
PIN FUNCTION
Symbol
Parameter
SO16N
DIP16
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
120
80
C/W
N.
Name
Function
1
C
SS
Soft Start Timing Capacitor
2
R
fstart
Soft Start Frequency Setting - Low Impedance Voltage Source - See also C
f
3
C
f
Oscillator Frequency Setting - see also R
fmin
, R
fstart
4
R
fmin
Minimum Oscillation Frequency Setting - Low Impedance Voltage Source - See also C
f
5
OP
out
Sense OP AMP Output - Low Impedance
6
OP
on-
Sense Op Amp Inverting Input - High Impedance
7
OP
on+
Sense Op Amp Non Inverting Input - High Impedance
8
EN1
Half Bridge Latched Enable
9
EN2
Half Bridge Unlatched Enable
10
GND
Ground
11
LVG
Low Side Driver Output
12
V
s
Supply Volatge with Internal Zener Clamp
13
N.C.
Not Connected
14
OUT
High Side Driver Reference
15
HVG
High Side Driver Output
16
V
boot
Bootstrapped Supply Voltage
Css
Rfstart
Cf
Rfmin
OPOUT
OPIN+
OPIN-
1
3
2
4
5
6
7
GND
V
S
LVG
N.C.
OUT
HVG
VBOOT
16
15
14
13
12
10
11
EN1
8
EN2
9
D98IN888
3/16
L6598
ABSOLUTE MAXIMUM RATINGS
(*) The device is provided of an internal Clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage
source.
Note : ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (Human Body Model).
RECOMMENDED OPERATING CONDITIONS
(*) If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580V.
Symbol
Parameter
Value
Unit
I
S
Supply Current at V
cl
(*)
25
mA
V
LVG
Low Side Output
14.6
V
V
OUT
High Side Reference
-1 to V
BOOT
-18
V
V
HVG
High Side Output
-1 to V
BOOT
V
V
BOOT
Floating Supply Voltage
618
V
dV
BOOT/dt
VBOOT pin Slew Rate (repetitive)
50
V/ns
dV
OUT/dt
OUT pin Slew Rate (repetitive)
50
V/ns
V
ir
Forced Input Voltage (pins Rfmin, Rfstart)
-0.3 to 5
V
V
ic
Forced Input Volatge (pins Css, Cf)
-0.3 to 5
V
V
EN1
, V
EN2
Enable Input Voltage
-0.3 to 5
V
I
EN1
, I
EN2
Enable Input Current
3
mA
V
opc
Sense Op Amp Common Mode Range
-0.3 to 5
V
V
opd
Sense Op Amp Differential Mode Range
-5 to 5
V
V
opo
Sense Op Amp Output Voltage (forced)
4.6
V
T
stg
Storage Temperature
-40 to +150
C
T
j
Junction Temperature
-40 to +150
C
T
amb
Ambient Temperature
-40 to +125
C
Symbol
Parameter
Value
Unit
V
S
Supply Voltage
10 to V
cl
V
V
out
(*)
High Side Reference
-1 to Vboot-V
cl
V
V
boot
(*)
Floating Supply Rail
500
V
f
max
Maximum Switching Frequency
400
kHz
L6598
4/16
ELECTRICAL CHARACTERISTCS (V
S
= 12V; V
BOOT
- V
OUT
= 12V; T
amb
= 25
C)
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
V
suvp
12
V
S
Turn On Threshold
10
10.7
11.4
V
V
suvn
V
S
Turn Off Threshold
7.3
8
8.7
V
V
suvh
Supply Voltage Under Voltage
hysteresis
2.7
V
V
cl
Supply Voltage Clamping
14.6
15.6
16.6
V
I
su
Start Up Current
V
s
< V
suvn
250
A
I
q
Quiescent Current, fout =
60kHz, no load
V
s
> V
suvp
2
mA
HIGH VOLTAGE SECTION
I
bootleak
16
BOOT pin Leakage Current
V
BOOT
= 580V
5
mA
I
outleak
14
OUT pin Leakage Current
V
OUT
= 562V
5
mA
R
don
16
Bootstrap Driver On Resistance
150
HIGH/LOW SIDE DRIVERS
I
hvgso
15
High Side Driver Source Current
V
HVG
-V
OUT
= 0
170
250
mA
I
hvgsi
High Side Driver Sink Current
V
HVG
-V
BOOT
= 0
300
450
mA
I
lvgso
11
Low Side Driver Source Current
V
LVG-GND
= 0
170
250
mA
I
lvgsi
Low Side Driver Sink Current
V
LVG - VS
= 0
300
450
mA
t
rise
15,11
Low/High Side Output Rise Time C
load
= 1nF
80
120
ns
t
fall
C
load
= 1nF
40
80
ns
OSCILL ATOR
DC
14
Output Duty Cycle
48
50
52
%
f
min
Minimum Output Oscillation
Frequency
C
f
= 470pF; R
fmin
= 50k
58.2
60
61.8
kHz
f
start
Soft Start Output Oscillation
Frequency
C
f
= 470pF; R
fmin
= 50k;
R
fstart
= 47k
114
120
126
kHz
V
ref
2, 4
Voltage to Current Converters
Threshold
2
2
t
d
14
Dead Time between Low and
High Side Conduction
0.2
0.27
0.35
s
TIMING SECTION
k
ss
1
Soft Start Timing constant
C
ss
= 330nF
0.115
0.15
0.185
s/
F
5/16
L6598
Figure 1. EN2 Timing Diagrams
SENSE OP AMP
l
IB
6, 7
Input Bias Current
0.1
A
V
io
Input Offset Voltage
-10
10
mV
R
out
5
Output Resistance
200
300
I
out-
Source Output Current
V
out
= 4.5V
1
mA
I
out+
Sink Output Current
V
out
= 0.2V
1
mA
V
ic
6,7
OP AMP input common mode
range
-0.2
3
V
GBW
Sense Op Amp Gain Band
Width Product
1
MHz
G
dc
DC Open Loop Gain
80
dB
COMPARATORS
V
the1
8
Enabling Comparator Threshold
0.56
0.6
0.64
V
V
the2
9
Enabling Comparator Threshold
1.05
1.2
1.35
V
t
pulse
8,9
Minimum Pulse lenght
200
ns
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
T
SS
f
start
f
min
EN2
V
Css
f
OUT
T
SS
D98IN889
ELECTRICAL CHARACTERISTCS (continued)
L6598
6/16
Figure 2. EN1 Timing Diagrams
Figure 3. Oscillator/Output Timing Diagram
High/Low Side driving section
An High and Low Side driving Section provide the proper driving to the external Power MOS or IGBT. An high
sink/source driving current (450/250 mA typ) ensure fast switching times also when size4 Power MOS are used.
The internal logic ensures a minimum dead time to avoid cross-conduction of the power devices.
Timing and Oscillator Section
The L6598 is provided of a soft start function. It consists in a period of time, T
SS
, in which the switching frequen-
cy shifts from f
start
to f
min
. This feature is explained in the following description (ref. fig.4 and fig.5).
EN1
EN2
LVG
HVG
D98IN890
LVG
HVG
C f
D98IN897
7/16
L6598
Figure 4. Soft Start and frequency shifting block
During the soft start time the current I
SS
charges the capacitor C
SS
, generating a voltage ramp which is delivered
to a transconductance amplifier, as shown in fig. 4. Thus this voltage signal is converted in a growing current
which is subtracted to I
fstart
. Therefore the current which drives the oscillator to set the frequency during the soft
start is equal to:
[1]
where
[2]
At the start-up (t=0) the L6598 oscillates at f
start
, set by:
[3]
At the end of soft start (t = T
SS
) the second term of eq.1 decreases to zero and the switching frequency is set
only by I
min
(i.e. R
fmin
):
[4]
Since the second term of eq.1 is equal to zero, we have:
[5]
Note that there is not a fixed threshold of the voltage across C
SS
in which the soft start finishes (i.e. the end of
the frequency shifting), and T
SS
depends on C
SS
, I
fstart
, g
m
, and I
SS
(eq. 5). Making T
SS
independent of I
fstart
,
the I
SS
current has been designed to be a fraction of I
fstart
, so:
[6]
In this way the soft start time depends only on the capacitor C
SS
. The typical value of the k
SS
constant (Soft
Css
Ifmin
Ifstart
Iss
gm
OSC
Iosc
I
osc
I
f min
I
f st art
g
m
V
Css
t
( )
(
)
+
I
f min
I
f st art
g
m
I
ss
C
ss
--------------
t
+
=
=
I
f min
V
R EF
R
f min
--------------
I
f sart
,
V
REF
R
f st art
----------------
V
R EF
,
2V
=
=
=
I
osc
0
( )
I
f min
I
f st art
+
V
R EF
1
R
fm in
--------------
1
R
fst art
----------------
+
=
=
I
osc
T
ss
(
)
I
f m in
V
REF
R
f min
--------------
=
=
I
fst art
g
m
I
ss
C
ss
--------------
T
SS
0
T
SS
C
ss
I
f st art
g
m
I
ss
------------------------
=
=
I
SS
I
f st art
K
--------------
T
SS
C
ss
I
f st art
g
m
I
f st art
K
--------------------------
T
SS
C
ss
g
m
K
-----------
T
SS
k
SS
C
SS
=
=
=
L6598
8/16
Start Timing Constant) is 0.15 s/
F.
The current I
osc
is fed to the oscillator as shown in fig. 5. It is twice mirrored (x4 and x8) generating the triangular
wave on the oscillator capacitor C
f
. Referring to the internal structure of the oscillator (fig.5), a good relationship
to compute an approximate value of the oscillator frequency in normal operation is:
[7]
The degree of approximation depends on the frequency value, but it remains very good in the range from 30kHz
to 100kHz (figg.6-10)
Figure 5. Oscillator Block
f
min
1.41
R
f min
C
f
--------------------
=
X 8
X 4
Iosc
Vth+
Vth-
S
R
Cf
+
+
9/16
L6598
Figure 6. Typ. fmin vs. Rfmin @ Cf = 470pF
Figure 7. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
Figure 8. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
Figure 9. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
Figure 10. fmin @ different Rf vs Cf
20
40
60
80
100 R
fmin
(K
)
20
40
60
80
100
f
min
(KHz)
D98IN891
20
40
60
80
100 R
fstart
(K
)
20
40
60
80
f
(KHz)
Rfmin=33K
D98IN892
20
40
60
80
100 R
fstart
(K
)
20
40
60
80
100
f
(KHz)
Rfmin=50K
D98IN893
20
40
60
80
100 R
fstart
(K
)
20
40
60
80
100
f
(KHz)
Rfmin=100K
D98IN894
Cf (pF)
400
0
200
0
200
400
fmin
(KHz)
Rf=90Kohm - calc.
Rf=19.9Kohm - calc.
Rf=90Kohm - meas.
Rf=19.9Kohm - meas.
L6598
10/16
Bootstrap Section
The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally re-
quires an high voltage fast recovery diode for charging the bootstrap capacitor (fig. 11a). In the L6568 a patent-
ed integrated structure, replaces this external diode. It is realised by means of a high voltage DMOS, driven
synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 11b.
Figure 11. ootstrap driver
To drive the synchronised DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is
obtained by means of an internal charge pump (fig. 11b).
The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. The introduction
of the diode prevents any current can flow from the V
boot
pin to the V
S
one in case that the supply is quickly
turned off when the internal capacitor of the pump is not fully discharged.
The bootstrap driver introduces a voltage drop during the recharging of the capacitor C
boot
(i.e. when the low
side driver is on), which increases with the frequency and with the size of the external power MOS. It is the sum
of the drop across the R
DSON
and of the diode threshold voltage. At low frequency this drop is very small and
can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing
the amplitude of the driving signal, can significantly increase the R
DSON
of the external power MOS (and so the
dissipation).
To be considered that in resonant power supplies the current which flows in the power MOS decreases increas-
ing the switching frequency and generally the increases of R
DSON
is not a problem because power dissipation
is negligible. The following equation is useful to compute the drop on the bootstrap driver:
[8]
where Q
g
is the gate charge of the external power MOS, R
dson
is the on resistance of the bootstrap DMOS, and
T
charge
is the time in which the bootstrap driver remains on (about the semiperiod of the switching frequency
minus the dead time). The typical resistance value of the bootstrap DMOS is 150 Ohm. For example using a
power MOS with a total gate charge of 30nC the drop on the bootstrap driver is about 3V, at a switching fre-
quency of 200kHz. In fact:
To summarise, if a significant drop on the bootstrap driver (at high switching frequency when large power MOS
are used) represents a problem, an external diode can be used, avoiding the drop on the R
DSON
of the DMOS.
V
S
V
BOOT
LVG
C
BOOT
V
OUT
V
S
V
BOOT
C
BOOT
V
OUT
D
BOOT
a
b
V
drop
I
ch
e
arg
R
dson
V
diode
V
drop
+
Q
g
T
ch
e
arg
-------------------
R
dson
V
diode
+
=
=
V
drop
30 nC
2.23
s
------------------
150
0.6V~2.6V
+
=
11/16
L6598
OP AMP Section
The integrated OP AMP is designed to offer Low Output Impedance, wide band, High input Impedance and wide
Common Mode Range. It can be readily used to implement protection features or a closed loop control. For this
purpose the OP AMP Output can be properly connected to R
fmin
pin to adjust the oscillation frequency.
Comparators
Two CMOS comparators are available to perform protection schemes. Short pulses (>= 200ns) on Comparators
Input are recognised. The EN1 input (active High), has a threshold of 0.6V (typical value) forces the L6598 in a
latched shut down state (e.g. LVG Low, HVG low, Oscillator stopped), as in the Under Voltage Conditions. Nor-
mal Operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with
a threshold of 1.2V (typical value) restarts a Soft Start sequence (see Timing Diagrams). In addition the EN2
Comparator, when activated, removes a latched shutdown caused by EN1.
Figure 12. Switching Time Waveform Definitions
Figure 13. Dead Time and Duty Cycle Waveform Definition
90%
90%
10%
10%
tf
tr
LVG
90%
90%
10%
10%
tf
tr
HVG
D98IN898
LVG
HVG
t d
50%
50%
t d
50%
50%
T1
50%
Tperiod
Dc =
Tperiod
T1
D98IN899
L6598
12/16
Figure 14. Typ. fmin vs. Temperature
Figure 15. Typ. fstart vs. Temperature
Figure 16. Vs thresholds and clamp vs temp.
Figure 17. Start Up Current vs Temperature
Figure 18. Quiescent Current vs Temperature
Figure 19. HVG Source and Sink Current vs.
Temperature
-50
0
50
100
40
50
60
70
T(
C)
f
min
(KHz)
D98IN895
-50
0
50
100
100
110
120
130
T(
C)
f
fstart
(KHz)
D98IN896
Vs
(V)
T (
C)
-50
0
50
100
6
8
10
12
14
Vclamp
Vsuvp
Vsuvn
-50
0
50
100
100
50
150
200
Isu
(
A)
T (
C)
-50
0
50
100
T (
C)
2.3
2.1
1.9
1.7
1.5
Iq @ 12V
Iq @ Vclamp
Iq
(mA)
-50
0
50
100
T (
C)
200
300
100
400
500
Ihvg source curr.
Ihvg sink curr.
Ihvg
(mA)
13/16
L6598
Figure 20. LVG Source and Sink Current vs.
Temperature
Figure 21. Soft Start Timing Constant vs.
Temperature
200
300
100
400
500
Ilvg
(mA)
-50
0
50
100
T (
C)
Ilvg source curr.
Ilvg sink curr.
-50
0
50
100
T (
C)
0.14
0.12
0.16
kss
(s/
F)
Figure 22. Wide Range AC/DC Adapter Application
L6561
85 to 270
Vac
Vo
TL431
VCO
&
CONTROL
DRIVER
L6598
ENABLE
D98IN874A
L6598
14/16
DIP16
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
OUTLINE AND
MECHANICAL DATA
15/16
L6598
SO16 Narrow
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.069
a1
0.1
0.25
0.004
0.009
a2
1.6
0.063
b
0.35
0.46
0.014
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.020
c1
45
(typ.)
D (1)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F (1)
3.8
4
0.150
0.157
G
4.6
5.3
0.181
0.209
L
0.4
1.27
0.016
0.050
M
0.62
0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8
(max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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L6598
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