90V BCD MIXED TECHNOLOGY
SO24 PLASTIC SMD PACKAGE
4.5 TO 13.2V OPERATIVE VOLTAGE
25 TO
35V OUTPUT VOLTAGE RANGE
SELECTABLE BY EXTERNAL RESISTORS
FULL-WAVE RESONANT DC-DC CON-
VERTER USING SINGLE COIL FOR DUAL
HIGH VOLTAGE GENERATOR WITH OUT-
PUT SLEW RATE CONTROL AND SELF
CURRENT LIMITING FOR LOW EMI
35V OR 0/+70V OPERATIVE VOLTAGE
DRIVING CONFIGURATION MODES:
1. SINGLE ENDED VOLTAGE MODE
2. DIFFERENTIAL VOLTAGE MODE
3. SINGLE ENDED CHARGE MODE
DOUBLE OPERATIONAL AMPLIFIERS WITH
500KHZ GAIN BANDWIDTH PRODUCT AND
LOAD DRIVING CAPABILITY FROM 0.4nF
UP TO 24nF
ANALOG VOLTAGE SHIFTING CIRCUITRY
INTERNAL 2.5V VOLTAGE REFERENCE
POWER SAVING SLEEP MODE
USER SPECIFIED INPUT REFERENCE
(2.25V DC)
DESCRIPTION
The L6660 is a piezoelectric actuator driver.
This is preliminary information on a new product now in development. Details are subject to change without notice.
December 2000
HVM
-35V
V512
+35V
Rfdb1
Rfdb2
HVP=VrefIN(1+Rfdb1/Rfdb2)
From DAC
OUTPUT
2.2nF
47
H
220nF
68nF
220nF
47nF
Rs
V5/12
1
K
1
K
HVP
HVM
-
+
1
K
1
K
HVP
HVM
-
+
B
A
Internal
Current
Bias
+
-
DC-DC LOGIC
Back-Up
Oscill.
:5
[12] GND-A
[21] Vfdb
[22] RCcomp
[2] GND-P
[3] COIL
[5] OUT1-A
[6] OUTK-A
[23] HVM
[19] OUT1-B
[18] OUTK-B
[24] HVP
MUX
Controll
Logic
Internal Band-gap
and 2.5 reference Voltage
Digital
Pwr Supply
Shifter
Vosh=Vin-Vref
SLEEP
[15] WENA
[17] INB(inv)
[16] INB(not inv)
[9] INA(not inv)
[8] INA(inv)
[4] AorB
[1] AandB
[20] V5/12AP
[14] IN Vref
[7] SLEEP
[10] Vosh
[11] Vin0-5
[13] Vref out
A-GND
100nF
BLOCK AND APPLICATION DIAGRAM
SO24(Shrink)
L6660
MILLI-ACTUATOR DRIVER
PRODUCT PREVIEW
1/9
A and B
GND-P
COIL
A or B.
OUT1-A
SLEEP
OUTK-A
INA(inv)
INA(not inv)
INB(not inv)
INB(inv)
OUTK-B
V5/12-AP
OUT1-B
RC comp
HVM
HVP
1
3
2
4
5
6
7
8
9
22
21
20
19
18
16
17
15
23
10
24
WENA
PINCON
Vin 0-5
Vref IN
11
14
13
12
GND-A
Vref OUT
V
OSH
V
FDB
PIN CONNECTION SO24-SHIRINK (Top view)
PIN FUNCTIONS
N.
Name
Description
1
AandB
MUX Enable (see Tab. 1).
2
GND-P
Power ground.
3
COIL
Coil for positive step UP and capacitor for negative charge.
4
AorB
MUX command Aor B input selection (0 = A; 1 = B).
5
OUT1-A
Output ampl.A.
6
OUTK-A
Hi current output ampl.A.
7
SLEEP
Sleep mode for stand-by condition (0=SLEEP 1=operative).
8
INA (inv)
Inverting input of A-amplifier.
9
INA (not inv)
Non Inverting input of A-amplifier.
10
Vosh
Analog level shifter output Vin-Vref (-2.5 to +2.5 dynamic range)
11
Vin 0-5
Analog level shifter input positive voltage.
12
GND-A
Analog ground.
13
V
ref
OUT
Precise 2.5V reference voltage.
14
V
ref
IN
Input for external reference voltage.
15
WENA
Multiplexer Enable, Falling Edge sensitive.
16
INB (not inv)
Non Inverting input of B-amplifier.
17
INB (inv)
Inverting input of B-amplifier.
18
OUTK-B
Hi current output ampl.B.
19
OUT1-B
Output ampl.B.
20
V5/12-AP
Analog&Power voltage supply 5 to 12V.
21
Vfdb
Feedback voltage for HVP regulator.
22
RC comp
DC-DC converter compensation network.
23
HVM
Negative High voltage generated op. amp. supply.
24
HVP
Positive High voltage generated op. amp. supply.
L6660
2/9
ELECTRICAL CHARACTERISTICS
(All the following parameters are specified @ 27C and V5/12 = 12V
5%, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
5/12
Main power supply
4.5
13.2
V
HVP
(1)
Output positive Voltage
Double Supply Voltage V
512
8
Double Supply Voltage V
512
< 8
27
18
35
35
V
V
Single Supply Voltage V
512
8
Single Supply Voltage V
512
< 8
27
18
70
35
V
V
HVripple
HVP, HVM ripple
Characterized only, Not Tested
External filter cap. 100nF
I
LOAD
= 0mA
0.8
V
I, hvp
Output current (see figure 1)
I, hvm
T
op
Time to operating condition
5
ms
F
switch
(2)
Switching Frequency
Refer to Block diagram
page1/10
300
kHz
R
ds, on
Boost transistor ON resistance
4
I
boost
Boost transistor current limiting
850
mA
V
sup
Minimum OpAmp supply
Voltage (HVP if externally
given)
Double Supply
V512
+4
V
Single Supply
V512
+4
V
DC gain
OpAmp DC gain
130
dB
GBW
OpAmp Gain Bandwidth
product
Cload 0.4nF to 24nF
Double Supply Voltage
500
KHz
DCinp
OpAmp Input dynamic voltage
Double supply
-3.5
4.5
V
Single supply
1.2
5
V
V
out
OpAmp Output dynamic voltage
Capacitive load
HVM
HVP
V
DC, I
bias
OpAmp Bias supply current
(both)
|HVP| = |HVM| = 35V
9
mA
I
out
(3)
OpAmp Dynamic Output
Average current with external
supply
-75
+75
mA
PSRR,P
OpAmp Positive power supply
rejection ratio
@ 50kHz not tested in production
-50
dB
PSRR,N
OpAmp Negative power supply
rejection ratio
@ 50kHz not tested in production
-50
dB
C
load
OpAmp Load capacitance
range
Voltage mode Gain min 20dB
0.4
24
nF
C
int
OpAmp Integration capacitance
Charge mode Gain min 20dB
0.4
24
nF
K
OpAmp Current ratio
OUTK/OUT1
9.8
10
10.2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V512
Supply voltage pin 17 referred to Ground
14
V
HVP
Positive high voltage referred to HVM
75
V
HVM
Negative high voltage referred to Ground
-38
V
IN A&B
Amplifier input voltage common mode
6
V
V
Maximum difference between pin 20 and pins 8, 9, 16 & 17
17
V
T
amb
Operative Ambient Temperature
-20 to +80
C
T
stg
Storage Temperature
-40 to +125
C
All the voltage value are referred to ground unless otherwise specified.
L6660
3/9
OPERATIONAL AMPLIFIERS DESCRIPTION
Each driver has two output stages scaled in cur-
rent by a factor K = 10.
In voltage mode configuration the two outputs are
shorted.
In charge mode configuration OUT1 drives a ca-
pacitor Cint and is closed in feedback, while
OUTK drives the piezo, mirroring the current sup-
plied to Cint, with a current multiplied by a K fac-
tor (see Fig.2).
The supply voltage can be internally generated
by the DC-DC converter, or external, maintaining
the DC-DC converter in sleep mode (PIN3
shorted to ground), in this case the supply volt-
age can be 0 to V5/12+4 minimum value up to
70V in single supply or V5/12+4 to 35V symmetri-
cal to ground.
The drivers have 130dB DC gain and the Band-
width is 500KHz. Stability is guaranteed with a
minimum gain of 20dB, for a capacitive load in
the range 0.4nF up to 24nF.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vout0
OpAmp Output Voltage with 0V
Input Voltage
External feedback programmed
for DC gain value <30V/V
-1
+1
V
V
ref
OUT
Reference Voltage PIN13
2.4
2.5
2.6
V
I
vref
Reference Voltage Output Current
-1
+1
mA
V
ref, cap
Filter capacitor at PIN13
10
100
nF
V
shifted
Voltage shift value
(V
PIN11
- V
PIN10
)
1.0V
Vin0-5
3.5V
V
ref
IN
-2%
V
ref
IN
V
ref
IN
+2%
V
Shifter Gain
Analog Voltage Shifter DC
Voltage Gain
V
10
V
11
V
PIN11
= V
REFIN
V'
10
V
PIN11
= V
REFIN
+ 0.1V
V"
10
G
=
V''
10
-
V'
10
0.1
0.975
1.00
1.025
BW
Vshift
Shifter circuitry Band Width
3dB amplitude drop
2
MHz
V
ref
IN
External reference voltage
(PIN14)
2.0
2.6
V
I
sleep
Total current in Sleep Mode
PIN7 at 0 logic
800
A
EAoff
DC-DC converter Error
Amplifier Input voltage Offset
(V
PIN14
-V
PIN21
)
V
ref
IN = 2.25V
-12
+12
mV
I
EA
Error amplifier Current
Capability
100
A
HVP%
Total HVP precision
V
ref
= 2.25V
0%
-4
+4
%
V
logic0
Voltage level for 0 logic at
digital input pin (Pin 1-4-7-15)
0.9
V
V
logic1
Voltage level for 1 logic at
digital input pin (Pin 1-4-7-15)
1.6
V
Z
time
Decay period for
V = |19V|
V
ref
(Pin14) = 2.25V See Fig. 3
0C < T
case
< 80C
140
340
s
T
op
Operative period from Not
Selected phase to Selected
phase for each driver
4
s
Note 1: Selectable by external resistors.
Note 2: Set by external Coil and Capacitor from 80 to 550KHz.
Note 3: Take into account the total power dissipation.
ELECTRICAL CHARACTERISTICS (continued)
22
24
26
28
30
32
34
36
1
5
9 13 17 21 25 29 33 37 41 45 49 53 57 61 65
Load DC Current (mA)
HV
P V
o
l
t
age
12V
11V
10V
9V
8V
7V
6V
5V
Figure 1. Load Regulation
L6660
4/9
The drivers can be supplied with HVP-HVM (dou-
ble supply mode) or with HVP-Ground (single
supply mode). In both cases they can achieve a
rail-to rail output dynamic range with an average
load current up to
75mA.
In double supply mode the input stage has -
5V/+5V common mode dynamic range, while in
single supply configuration it has 1.2V up to 10V
input common mode dynamic range.
-
+
HVP
HVM
Rb
1
1
K
K
C
Qpiezo=K*[Cint*(1+Ra/Rb)+C]*Vdac
Qpiezo=Cost*Vdac
Cost=k*[Cint*(1+Ra/Rb)+C]
Vdac
D98IN970A
Ra
R
P
Cpiezo
Cint
Figure 2. Charge Mode Configuration (configuration example; the final application depends on
user needs according with Electrical Characteristics).
Input Multiplexer
MULTIPLEXER is controlled by internal logic with 3 digital inputs, supplied by IntVref (2.5V), it is com-
patible to 3.3V and 5V logic command signals, it allows to perform the following configuration:
Table 1.
AandB
(PIN1)
AorB
(PIN4)
WENA
(PIN15)
INA+Status
INB+Status
Comment
0
1
X
INA+
connected to AGND
INB+
connected to AGND
Both drv. inp. are disconnected from ext
PIN and are connected to AGND
0
0
X
INA+
connected to PIN9
INB+
connected to PIN16
Both drv. inp. are accesible
(MUX is transparent)
1
1
1
INA+
connected to PIN9
INB+
connected to AGND
INA is selected
1
0
1
INA+
connected to AGND
INB+
connected to PIN16
INB is selected
1
1
(F.E.)
INA+
connected to PIN9
INB+
connected to AGND
From WENA Falling Edge, changes on
AorB (pin 4) will not change MUX state.
1
0
(F.E.)
INA+
connected to AGND
INB+
connected to PIN16
From WENA Falling Edge, changes on
AorB (pin 4) will not change MUX state.
F.E. = Falling Edge
The MUX is at NOT inv. Inputs, and NO current flows through the MUX switches, because the driver in-
put stage is designed with high impedance stage.
L6660
5/9
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