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L6712
L6712A
March 2004
2 PHASE OPERATION WITH
SYNCHRONOUS RECTIFIER CONTROL
ULTRA FAST LOAD TRANSIENT RESPONSE
INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
3 BIT PROGRAMMABLE OUTPUT FROM
0.900V TO 3.300V OR WITH EXTERNAL REF.
0.9% OUTPUT VOLTAGE ACCURACY
3mA CAPABLE AVAILABLE REFERENCE
INTEGRATED PROGRAMMABLE REMOTE
SENSE AMPLIFIER
PROGRAMMABLE DROOP EFFECT
10% ACTIVE CURRENT SHARING ACCURACY
DIGITAL 2048 STEP SOFT-START
CROWBAR LATCHED OVERVOLTAGE PROT.
NON-LATCHED UNDERVOLTAGE PROT.
OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S R
dsON
OR A
SENSE RESISTOR
OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 150kHZ
POWER GOOD OUTPUT AND INHIBIT FUNCTION
PACKAGES: SO-28 & VFQFPN-36
APPLICATIONS
HIGH CURRENT DC/DC CONVERTERS
DISTRIBUTED POWER SUPPLY
DESCRIPTION
The device implements a dual-phase step-down con-
troller with a 180 phase-shift between each phase
optimized for high current DC/DC applications.
Output voltage can be programmed through the in-
tegrated DAC from 0.900V to 3.300V; program-
ming the "111" code, an external reference from
0.800V to 3.300V is used for the regulation.
Programmable Remote Sense Amplifier avoids
use of external resistor divider and recovers loss-
es along distribution line.
The device assures a fast protection against load
over current and Over / Under voltage.An internal
crowbar is provided turning on the low side mosfet
if Over-voltage is detected.
Output current is limited working in Constant Cur-
rent mode: when Under Voltage is detected, the
device resets, restarting operation.
SO28
VFQFPN-36 (6x6x1.0)
ORDERING NUMBERS:
Package
Tube
Tape & Reel
SO
L6712D, L6712AD
L6712DTR, L6712ADTR
VFQFPN L6712Q, L6712AQ
L6712QTR, L6712AQTR
TWO-PHASE INTERLEAVED DC/DC CONTROLLER
BLOCK DIAGRAM
CURRENT
READING
I
DR
O
O
P
TOTAL
CURRENT
CURR
E
N
T
AVG
CH1
OCP
DAC
LO
G
I
C
P
W
M
AD
APT
I
V
E
A
N
T
I
C
R
O
S
S
CO
ND
UC
TI
O
N
CH1 OCP
2
PH
ASE
O
S
C
I
LLA
T
O
R
PWM1
CU
RR
E
N
T
CO
RRE
CT
I
O
N
ERROR
AMPLIFIER
REMOTE
AMPLIFIER
LS
LS
HS
Vcc
HS
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
Vcc
COMP
FB
VSEN
FBG
FBR
VID0
VID1
VID2
OSC / INH
SGND
VCCDR
VCCDR
VCC
LOGIC AND
PROTECTIONS
PWM2
CU
RR
E
N
T
CO
R
R
E
C
T
I
O
N
CH2
OCP
CURRENT
READING
LO
G
I
C
P
W
M
A
D
AP
TI
VE
AN
TI
CRO
SS
C
O
ND
UC
TI
ON
REF_IN/OUT
PGOOD
DROOP
BAND-GAP
REFERENCE
DIGITAL
SOFT-START
CH2 OCP
V
PROG
I
FB
_
S
T
A
R
T
CURRENT
READING
I
DR
O
O
P
TOTAL
CURRENT
CURR
E
N
T
AVG
CH1
OCP
DAC
LO
G
I
C
P
W
M
AD
APT
I
V
E
A
N
T
I
C
R
O
S
S
CO
ND
UC
TI
O
N
CH1 OCP
2
PH
ASE
O
S
C
I
LLA
T
O
R
PWM1
CU
RR
E
N
T
CO
RRE
CT
I
O
N
ERROR
AMPLIFIER
REMOTE
AMPLIFIER
LS
LS
HS
Vcc
HS
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
Vcc
COMP
FB
VSEN
FBG
FBR
VID0
VID1
VID2
OSC / INH
SGND
VCCDR
VCCDR
VCC
LOGIC AND
PROTECTIONS
PWM2
CU
RR
E
N
T
CO
R
R
E
C
T
I
O
N
CH2
OCP
CURRENT
READING
LO
G
I
C
P
W
M
A
D
AP
TI
VE
AN
TI
CRO
SS
C
O
ND
UC
TI
ON
REF_IN/OUT
PGOOD
DROOP
BAND-GAP
REFERENCE
DIGITAL
SOFT-START
CH2 OCP
V
PROG
I
FB
_
S
T
A
R
T
L6712A L6712
2/27
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION (Top view)
Symbol
Parameter
Value
Unit
V
CC
, V
CCDR
To PGND
15
V
V
BOOT
-V
PHASE
Boot Voltage
15
V
V
UGATE1
-V
PHASE1
V
UGATE2
-V
PHASE2
15
V
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
-0.3 to Vcc+0.3
V
VID0 to VID2
-0.3 to 5
V
All other pins to PGND
-0.3 to 7
V
V
PHASEx
Sustainable Peak Voltage. T<20ns @ 600kHz
26
V
UGATEX Pins
Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002"Human Body Model"
Acceptance Criteria: "Normal Performance"
1500
V
OTHER PINS
2000
V
Symbol
Parameter
SO28
VFQFPN36
Unit
R
thj-amb
Thermal Resistance Junction to Ambient
4 layer PCB (2s2p)
60
30
C/W
T
max
Maximum junction temperature
150
150
C
T
stg
Storage temperature range
-40 to 150
-40 to 150
C
T
j
Junction Temperature Range
-40 to 125
-40 to 125
C
P
MAX
Max power dissipation at T
amb
= 25
C
2
3.5
W
1
2
3
4
5
6
7
8
9
27
26
25
24
23 22 21
20
19
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
N.
C
.
FB
G
FB
R
VI
D
0
VI
D
1
VI
D
2
P
GOO
D
B
OOT
2
DRO
O
P
FB
CO
M
P
SG
N
D
SG
N
D
VC
C
N.
C
.
B
OOT1
N.C
N.C.
REF_IN/OUT
VSEN
ISEN1
PGNDS1
PGNDS2
ISEN2
N.C.
OSC
UGATE1
PHASE1
VCCDR
LGATE1
PGND
PGND
LGATE2
PHASE2
UGATE2
1
2
3
4
5
6
7
8
9
27
26
25
24
23 22 21
20
19
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
N.
C
.
N.C.
REF_IN/OUT
VSEN
ISEN1
PGNDS1
PGNDS2
ISEN2
N.C.
OSC
PHASE1
VCCDR
LGATE1
PGND
PGND
LGATE2
PHASE2
SO28
VFQFPN-36
Corner Pin internally connected to the Exposed Pad.
LGATE1
VCCDR
PHASE1
FB
BOOT1
UGATE1
DROOP
VCC
SGND
COMP
ISEN1
PGNDS1
REF_IN/OUT
VSEN
VID1
VID0
FBR
VID2
BOOT2
PGOOD
UGATE2
PHASE2
LGATE2
PGND
OSC/INH/FAULT
ISEN2
PGNDS2
FBG
1
3
2
4
5
6
7
8
9
18
17
16
15
19
20
10
11
12
13
14
24
23
22
21
25
26
27
28
3/27
L6712A L6712
ELECTRICAL CHARACTERISTCS
(V
CC
= 12V10%, T
J
= 0C to 70C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vcc SUPPLY CURRENT
I
CC
VCC supply current
HGATEx and LGATEx open
VCCDR=BOOTx=12V
7.5
10
12.5
mA
I
CCDR
VCCDR supply current
LGATEx open; VCCDR=12V
1.5
3
4
mA
I
BOOTx
Boot supply current
HGATEx open; PHASEx to
PGND; VCC=BOOTx=12V
0.5
1
1.5
mA
POWER-ON
Turn-On VCC threshold
VCC Rising; VCCDR=5V
8.2
9.2
10.2
V
Turn-Off VCC threshold
VCC Falling; VCCDR=5V
6.5
7.5
8.5
V
Turn-On VCCDR
Threshold
VCCDR Rising
VCC=12V
4.2
4.4
4.6
V
Turn-Off VCCDR
Threshold
VCCDR Falling
VCC=12V
4.0
4.2
4.4
V
OSCILLATOR AND INHIBIT
f
OSC
Initial Accuracy
OSC = OPEN
OSC = OPEN; Tj=0
C to 125C
135
127
150
165
178
kHz
kHz
INH
Inhibit threshold
I
SINK
=5mA
0.5
V
d
MAX
Maximum duty cycle
L6712, OSC = OPEN: I
DROOP
=0
OSC = OPEN; I
DROOP
=70
A
72
30
80
40
-
-
%
%
L6712A, OSC = OPEN
85
90
%
Vosc
Ramp Amplitude
3
V
FAULT
Voltage at pin OSC
OVP Active
4.75
5.0
5.25
V
REFERENCE AND DAC
V
OUT
(1)
Output Voltage Accuracy
VIDx See Table 1, VID
"11x"
-0.9
-
0.9
%
VID = "110"
-1.0
-
1.0
%
REF_IN/OUT
Reference Accuracy
VIDx See Table 1, VID
"111"
V
OUT
-5
V
OUT
V
OUT
+5
mV
Current Capability
3
mA
Load Regulation
I
REF
= from 0 to 3mA
5.0
mV
V
PROG
/ REF_IN/
OUT
Accuracy with external
reference
VID="111";
REF_IN/OUT = 0.8V to 3.3V
-2.0
2.0
%
REF_IN/OUT
Input impedance
400
k
I
VID
VID pull-up Current
VIDx =SGND
5
A
V
VID
VID pull-up Voltage
VIDx = OPEN
3
V
VID
IL
VID Input Levels
Input Low
0.4
V
VID
IH
Input High
1.0
V
ERROR AMPLIFIER
V
OS_EA
Offset
FB = COMP
-5
5
mV
DC Gain
80
dB
SR
Slew-Rate
COMP=10pF
15
V/
s
I
FB_START
Start-up Current
FB=SGND; During Soft Start...
65
A
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
V
OS_RA
Offset
VSEN = FBG
-8
8
mV
L6712A L6712
4/27
Note:
1. Output voltage is specified including Error Amplifier Offset in the trimming chain. Remote Amplifier is not included.
Table 1. Voltage Identification (VID) Codes.
DC Gain
80
dB
SR
Slew Rate
VSEN = 10pF
15
V/
s
DIFFERENTIAL CURRENT SENSING
I
ISEN1
, I
ISEN2
Bias Current
I
LOAD
= 0
45
50
55
A
I
PGNDSx
Bias Current
45
50
55
A
I
ISEN1
, I
ISEN2
Bias Current at
Over Current Threshold
80
85
90
A
I
DROOP
Droop Current
I
LOAD
0
0
1
A
I
LOAD
= 100%
47.5
50
52.5
A
GATE DRIVERS
t
RISE HGATE
High Side
Rise Time
BOOTx-PHASEx=10V;
C
HGATEx
to PHASEx=3.3nF
15
30
ns
I
HGATEx
High Side
Source Current
BOOTx-PHASEx=10V 2
A
R
HGATEx
High Side
Sink Resistance
BOOTx-PHASEx=12V;
1.5
2
2.5
t
RISE LGATE
Low Side
Rise Time
VCCDR=10V;
C
LGATEx
to PGNDx=5.6nF
30
55
ns
I
LGATEx
Low Side
Source Current
VCCDR=10V
1.8
A
R
LGATEx
Low Side
Sink Resistance
VCCDR=12V
0.7
1.1
1.5
PROTECTIONS
PGOOD
Upper Threshold
VSEN Rising
108
112
115
%
Lower Threshold
VSEN Falling
84
88
92
%
OVP
Over Voltage Threshold
VSEN Rising
115
122
130
%
UVP
Under Voltage Trip
VSEN Falling
55
60
65
%
V
PGOODL
PGOOD Voltage Low
I
PGOOD
= -4mA
0.4
V
I
PGOODH
PGOOD Leakage
V
PGOOD
= 5V
1
A
VID2
VID1
VID0
Output Voltage (V)
1
1
1
Ext. Ref.
1
1
0
0.900
1
0
1
1.250
1
0
0
1.500
0
1
1
1.715
0
1
0
1.800
0
0
1
2.500
0
0
0
3.300
ELECTRICAL CHARACTERISTCS (continued)
(V
CC
= 12V10%, T
J
= 0C to 70C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
5/27
L6712A L6712
PIN FUNCTION
N. (*)
Name
Description
SO
VFQFPN
1
33
LGATE1
Channel 1 LS driver output.
A little series resistor helps in reducing device-dissipated power.
2
34
VCCDR
LS drivers supply: it can be varied from 5V to 12V buses.
Filter locally with at least 1
F ceramic cap vs. PGND.
3
35
PHASE1
Channel 1 HS driver return path. It must be connected to the HS1 mosfet source
and provides the return path for the HS driver of channel 1.
4
36
UGATE1
Channel 1 HS driver output.
A little series resistor helps in reducing device-dissipated power.
5
2
BOOT1
Channel 1 HS driver supply. This pin supplies the relative high side driver.
Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode
to VCC (cathode vs. boot).
6
4
VCC
Device supply voltage. The operative supply voltage is 12V 10%.
Filter with 1
F (Typ.) capacitor vs. GND.
7
5,6
SGND
All the internal references are referred to this pin. Connect it to the PCB signal
ground.
8
7
COMP
This pin is connected to the error amplifier output and is used to compensate the
control feedback loop.
9
8
FB
This pin is connected to the error amplifier inverting input and is used to
compensate the control feedback loop.
10
9
DROOP
A current proportional to the sum of the current sensed in both channel is
sourced from this pin (50
A at full load, 70A at the Constant Current threshold).
Short to FB to implement the Droop effect: the resistor connected between FB
and VSEN (or the regulated output) allows programming the droop effect.
Otherwise, connect to GND directly or through a resistor (43k
max) and filter
with 1nF capacitor. In this last case, current information can be used for other
purposes.
11
11
REF_IN /
OUT
Reference input/output. Filter vs. GND with 1nF ceramic capacitor (a total of
100nF capacitor is allowed).
It reproduces the reference used for the regulation following VID code: when
VID=111, the reference for the regulation must be connected on this pin.
References ranging from 0.800V up to 3.300V can be accepted.
12
12
VSEN
Connected to the output voltage it is able to manage Over & Under-voltage
conditions and the PGOOD signal. It is internally connected with the output of the
Remote Sense Amplifier for Remote Sense of the regulated voltage.
Connecting 1nF capacitor max vs. GND can help in reducing noise injection at
this pin.
If no Remote Sense is implemented, connect it directly to the regulated voltage in
order to manage OVP, UVP and PGOOD.
13
13
ISEN1
Channel 1 current sense pin. The output current may be sensed across a sense
resistor or across the low-side mosfet R
dsON.
This pin has to be connected to the
low-side mosfet drain or to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as
possible to the PGNDS net in order to couple in common mode any picked-up
noise.
14
14
PGNDS1
Channel 1 Power Ground sense pin. The net connecting the pin to the sense
point must be routed as close as possible to the ISEN1 net in order to couple in
common mode any picked-up noise.
15
15
PGNDS2
Channel 2 Power Ground sense pin. The net connecting the pin to the sense
point must be routed as close as possible to the ISEN2 net in order to couple in
common mode any picked-up noise.
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