1/33

L6919E

September 2003

2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL

ULTRA FAST LOAD TRANSIENT RESPONSE

INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT

TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT FROM 0.800V TO 1.550V WITH
25mV STEPS

DYNAMIC VID MANAGEMENT

0.6% OUTPUT VOLTAGE ACCURACY

10% ACTIVE CURRENT SHARING ACCURACY

DIGITAL 2048 STEP SOFT-START

OVERVOLTAGE PROTECTION

OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S R

dsON

OR A

SENSE RESISTOR

OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 200kHz

POWER GOOD OUTPUT AND INHIBIT
FUNCTION

REMOTE SENSE BUFFER

PACKAGE: SO-28

APPLICATIONS

POWER SUPPLY FOR SERVERS AND
WORKSTATIONS

POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS

DISTRIBUTED POWER SUPPLY

DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC
conversion for high current microprocessors. The
device implements a dual-phase step-down con-
troller with a 180° phase-shift between each
phase. A precise 5-bit digital to analog converter
(DAC) allows adjusting the output voltage from
0.800V to 1.550V with 25mV binary steps manag-
ing On-The-Fly VID code changes.
The high precision internal reference assures the
selected output voltage to be within ±0.6%. The
high peak current gate drive affords to have fast
switching to the external power mos providing low
switching losses.
The device assures a fast protection against load
over current and load over/under voltage. An inter-
nal crowbar is provided turning on the low side
mosfet if an over-voltage is detected. In case of
over-current, the system works in Constant Cur-
rent mode.

SO-28

ORDERING NUMBERS:L6919E

L6919ETR

5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER

WITH DYNAMIC VID MANAGEMENT

BLOCK DIAGRAM

C U R R EN T

R EA D IN G

TO TAL

C UR REN T

CUR

C H1
O C P

D A C

DIGIT AL

SOFT- START

I
C

I
VE

I
O

C H1 OCP

2 P

I
L

PW M1

I
O

ERR OR

A MPL IF IER

R EMO TE

BU FFE R

3 2k

32k

L S

H S

Vc c

H S

BOO T 1

GA T E1

PHAS E1

L GAT E1

ISE N1

PGN DS1

PGN D

PGN DS2

ISE N2

L GAT E2

PHAS E2

U GA T E2

BOO T 2

V c c

COM P

V S EN

FB G

FB R

VID 0

VID 1

VID 2

VID 3

VID 4

PGO O D

O S C / I NH

S GN D

VC C D R

32k

V CC DR

V CC

I
C A

I
O

CH 2 OC P

PW M2

RRE

I
O

C H2

O C P

C U R R EN T

R EA D IN G

I
C

I
V

CRO

I
O

C U R R EN T

R EA D IN G

C U R R EN T

R EA D IN G

TO TAL

C UR REN T

CUR

C H1
O C P

D A C

DIGIT AL

SOFT- START

I
C

I
VE

I
O

I
C

I
VE

I
O

C H1 OCP

2 P

I
L

PW M1

I
O

ERR OR

A MPL IF IER

R EMO TE

BU FFE R

3 2k

32k

L S

H S

Vc c

H S

BOO T 1

GA T E1

PHAS E1

L GAT E1

ISE N1

PGN DS1

PGN D

PGN DS2

ISE N2

L GAT E2

PHAS E2

U GA T E2

BOO T 2

V c c

COM P

V S EN

FB G

FB R

VID 0

VID 1

VID 2

VID 3

VID 4

PGO O D

O S C / I NH

S GN D

VC C D R

32k

V CC DR

V CC

I
C A

I
O

CH 2 OC P

PW M2

RRE

I
O

C H2

O C P

C U R R EN T

R EA D IN G

C U R R EN T

R EA D IN G

I
C

I
V

CRO

I
O

I
C

I
V

CRO

I
O

L6919E

2/33

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

PIN CONNECTION

Symbol

Parameter

Value

Unit

Vcc, V

CCDR

to PGND

BOOT

-V

PHASE

Boot Voltage

UGATE1

-V

PHASE1

UGATE2

-V

PHASE2

LGATE1, PHASE1, LGATE2, PHASE2 to PGND

-0.3 to Vcc+0.3

VID0 to VID4

-0.3 to 5

All other pins to PGND

-0.3 to 7

phase

Sustainable Peak Voltage t < 20ns @ 600kHz

UGATEx Pin

Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002"Human Body Model"
Acceptance Criteria: "Normal Performance"

±1000

OTHER PINS

±2000

Symbol

Parameter

Value

Unit

th j-amb

Thermal Resistance Junction to Ambient

C/W

max

Maximum junction temperature

150

storage

Storage temperature range

-40 to 150

Junction Temperature Range

0 to 125

°C

MAX

Max power dissipation at T

amb

= 25°C

LGATE1

VCCDR

PHASE1

BOOT1

UGATE1

VSEN

VCC

SGND

COMP

ISEN1

PGNDS1

FBR

FBG

VID3

VID2

VID1

VID4

BOOT2

PGOOD

UGATE2

PHASE2

LGATE2

PGND

OSC / INH / FAULT

ISEN2

PGNDS

VID0

L69

19E

3/33

L6919E

ELECTRICAL CHARACTERISTICS
V

= 12V ±15%, T

= 0 to 70°C unless otherwise specified

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Vcc SUPPLY CURRENT

Vcc supply current

HGATEx and LGATEx open
V

CCDR

BOOT

=12V

7.5

12.5

CCDR

supply current

LGATEx open; V

CCDR

=12V

BOOTx

Boot supply current

HGATEx open; PHASEx to PGND
V

BOOT

=12V

0.5

1.5

POWER-ON

Turn-On V

threshold

Rising; V

CCDR

=5V

8.2

9.2

10.2

Turn-Off V

threshold

Falling; V

CCDR

=5V

6.5

7.5

8.5

Turn-On V

CCDR

Threshold

CCDR

Rising

=12V

4.2

4.4

4.6

Turn-Off V

CCDR

Threshold

CCDR

Falling

=12V

4.0

4.2

4.4

OSCILLATOR/INHIBIT/FAULT

OSC

Initial Accuracy

OSC = OPEN
OSC = OPEN; Tj=0

C to 125

135
127

150

165
178

kHz
kHz

INH

Inhibit threshold

SINK

=5mA

0.5

MAX

Maximum duty cycle

OSC = OPEN; I

= 0

OSC = OPEN; I

= 70

Vosc

Ramp Amplitude

FAULT

Voltage at pin OSC

OVP or UVP Active

4.75

5.0

5.25

REFERENCE AND DAC

Output Voltage
Accuracy

VID0, VID1, VID2, VID3, VID4
see Table1;
FBR = V

OUT

; FBG = GND

-0.6

0.6

DAC

VID pull-up Current

VIDx = GND

VID pull-up Voltage

VIDx = OPEN

2.9

3.3

ERROR AMPLIFIER

DC Gain

Slew-Rate

COMP=10pF

DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)

DC Gain

V/V

CMRR

Common Mode Rejection Ratio

Slew Rate

VSEN=10pF

L6919E

4/33

DIFFERENTIAL CURRENT SENSING

ISEN1

ISEN2

Bias Current

LOAD

= 0

PGNDSx

Bias Current

ISEN1

ISEN2

Bias Current at
Over Current Threshold

Active Droop Current

LOAD

= 100%

47.5

52.5

GATE DRIVERS

RISE

HGATE

High Side
Rise Time

BOOTx

-V

PHASEx

=10V;

HGATEx

to PHASEx=3.3nF

HGATEx

High Side
Source Current

BOOTx

-V

PHASEx

=10V 2

HGATEx

High Side
Sink Resistance

BOOTx

-V

PHASEx

=12V;

1.5

2.5

RISE

LGATE

Low Side
Rise Time

CCDR

=10V;

LGATEx

to PGNDx=5.6nF

LGATEx

Low Side
Source Current

CCDR

=10V

1.8

LGATEx

Low Side
Sink Resistance

CCDR

=12V

0.7

1.1

1.5

PROTECTIONS

PGOOD

Upper Threshold
(V

SEN

/DAC Output)

SEN

Rising

108

112

116

PGOOD

Lower Threshold
(V

SEN

/DAC Output)

SEN

Falling

OVP

Over Voltage Threshold
(V

SEN

)

SEN

Rising

1.915

2.05

UVP

Under Voltage Trip
(V

SEN

/DAC Output)

SEN

Falling

PGOODL

PGOOD Voltage Low

PGOOD

= -4mA

0.4

PGOODH

PGOOD Leakage

PGOOD

= 5V

ELECTRICAL CHARACTERISTICS (continued)
V

= 12V ±15%, T

= 0 to 70°C unless otherwise specified

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

5/33

L6919E

Table 1. Voltage Identification (VID) Codes

The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor

Reference Schematic

VID4 VID3

VID2

VID1

VID0

Output

Voltage (V)

VID4 VID3

VID2

VID1

VID0

Output

Voltage (V)

1.575

1.175

1.550

1.150

1.525

1.125

1.500

1.100

1.475

1.075

1.450

1.050

1.425

1.025

1.400

1.000

1.375

0.975

1.350

0.950

1.325

0.925

1.300

0.900

1.275

0.875

1.250

0.850

1.225

0.825

1.200

Shutdown

PGOOD

PGND

PGNDS2

ISEN2

LGATE2

VSEN

PHASE2

UGATE2

BOOT2

VCC

COMP

SGND

OSC / INH

VID0

VID1

VID2

VID3

VID4

PGNDS1

ISEN1

LGATE1

PHASE1

UGATE1

BOOT1

VCCDR

FBR

FBG

LS2

HS2

OUT

LS1

HS1

Vin

GNDin

PGOOD

L6919E

LOAD

L6919E

6/33

PIN FUNCTION

Name

Description

LGATE1

Channel 1 LS driver output.
A little series resistor helps in reducing device-dissipated power.

VCCDR

LS drivers supply: it can be varied from 5V to 12V buses.
Filter locally with at least 1

F ceramic cap vs. PGND.

PHASE1

Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides
the return path for the HS driver of channel 1.

UGATE1

Channel 1 HS driver output.
A little series resistor helps in reducing device-dissipated power.

BOOT1

Channel 1 HS driver supply. This pin supplies the relative high side driver.
Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC
(cathode vs. boot).

VCC

Device supply voltage. The operative supply voltage is 12V ±10%.
Filter with 1

F (Typ.) capacitor vs. GND.

GND

All the internal references are referred to this pin. Connect it to the PCB signal ground.

COMP

This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.

This pin is connected to the error amplifier inverting input and is used to compensate the
voltage control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50

A at full load, 70

A at the Constant Current threshold). Connecting a resistor between this

pin and VSEN pin allows programming the droop effect.

VSEN

Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with
the output of the Remote Sense Buffer for Remote Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
Connecting 1nF capacitor max vs. SGND can help in reducing noise injection.

FBR

Remote sense buffer non-inverting input. It has to be connected to the positive side of the load
to perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).

FBG

Remote sense buffer inverting input. It has to be connected to the negative side of the load to
perform a remote sense.
Pull-down to ground if no remote sense is implemented.

ISEN1

Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet R

dsON.

This pin has to be connected to the low-side mosfet drain or

to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS net in order to couple in common mode any picked-up noise.

PGNDS1

Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
noise.

PGNDS2

Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
noise.

ISEN2

Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet R

dsON.

This pin has to be connected to the low-side mosfet drain or

to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS net in order to couple in common mode any picked-up noise.

7/33

L6919E

OSC/INH

FAULT

Oscillator pin.
It allows programming the switching frequency of each channel: the equivalent switching
frequency at the load side results in being doubled.
Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from
(into) the pin with an internal gain of 6kHz/

A (See relevant section for details). If the pin is not

connected, the switching frequency is 150kHz for each channel (300kHz on the load).
The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this
condition, cycle VCC.
Forcing the pin to a voltage lower than 0.6V, the device stop operation and enter the inhibit
state.

18-22

VID4-0

Voltage IDentification pins.
Internally pulled-up, connect to GND to program a `0' while leave floating to program a `1'.
They are used to program the output voltage as specified in Table 1 and to set the PGOOD,
OVP and UVP thresholds.
The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of
any external set-up resistor.

PGOOD

This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds and during soft start. It cannot be pulled-up above 5V.
If not used may be left floating.

BOOT2

Channel 2 HS driver supply. This pin supplies the relative high side driver.
Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC
(cathode vs. boot).

UGATE2

Channel 2 HS driver output.
A little series resistor helps in reducing device-dissipated power.

PHASE2

Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides
the return path for the HS driver of channel 2.

LGATE2

Channel 2 LS driver output.
A little series resistor helps in reducing device-dissipated power.

PGND

LS drivers return path.
This pin is common to both sections and it must be connected through the closest path to the
LS mosfets source pins in order to reduce the noise injection into the device.

PIN FUNCTION (continued)

Name

Description

L6919E

8/33

DEVICE DESCRIPTION
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for
a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is de-
signed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is
provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and
the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.825V to
1.575V with 25mV binary steps, with a maximum tolerance of ±0.6% over temperature and line voltage variations. The
device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor.
The device manages On-The-Fly VID Code changes stepping to the new configuration following the VID table with no
need for external components. The device provides an average current-mode control with fast transient response. It
includes a 150kHz free-running oscillator. The error amplifier features a 15V/

s slew rate that permits high converter

bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a
sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the av-
erage current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and
dynamic conditions. The device protects against Over-Current, with an OC threshold for each phase, entering in con-
stant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the
bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the
FAULT pin is driven high. The device performs also Over-Voltage protection that disables immediately the device turn-
ing ON the lower driver and driving high the FAULT pin.

OSCILLATOR
The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so
that the resulting switching frequency at the load side results in being doubled.
The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant cur-
rent an internal capacitor. The current delivered to the oscillator is typically 25 A (Fsw=150kHz) and may be varied
using an external resistor (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at
fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin con-
sidering the internal gain of 6KHz/

In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC
to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:

Note that forcing a 25

A into this pin, the device stops switching because no current is delivered to the oscillator.

Figure 1. R

OSC

vs. Switching Frequency

O SC

vs. GND: f

150 kHz

1.237

O SC

---------------

kH z

-----------

150kHz

7.422 10

O SC

(

)

------------------------------

O SC

vs. 12V: f

150kHz

1.237

O SC

---------------------------

kHz

-----------

150 kHz

6.457 10

O SC

(

)

------------------------------

2000

4000

6000

8000

10000

12000

14000

100

125

150

Frequency (KHz)

sc(

) v

.
1

100

200

300

400

500

600

700

800

150

250

350

450

550

650

Frequency (KHz)

sc(

)
vs.

9/33

L6919E

DIGITAL TO ANALOG CONVERTER

The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with
25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of
±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is pro-
grammed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code
drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an
amplifier obtaining the V

PROG

voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are

provided (realized with a 5

A current generator up to 3.0V Typ); in this way, to program a logic "1" it is enough

to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the
"11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are disabled.
The condition is latched.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over
/ Under Voltage protection (OVP/UVP) thresholds.

DYNAMIC VID TRANSITION

The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during nor-
mal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code
modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in
25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes
are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked dur-
ing the transition and it is re-activated after the transition has finished while OVP / UVP are still active.

Figure 2. Dynamic VID transition

DRIVER SECTION

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the
R

dsON

), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for
the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VC-
CDRV pin is required to start operations of the device.

The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction
time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanosec-
onds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side
mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate
drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When
it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the
inductor is negative, the source of high-side mosfet will never drop.

VID

Reference

OUT

1 Clock Cycle Blanking Time

25mV steps transition

L6919E

10/33

Figure 3. Drivers peak current: High Side (left) and Low Side (right)

To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source
of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the neg-
ative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is
negative.

The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND
pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply
for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several com-
bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion
is also flexible; 5V or 12V bus can be chosen freely.

The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-
itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with
V

BOOT -VPHASE

= 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with

VCCDR = 12V.

CURRENT READING AND OVER CURRENT

The current flowing trough each phase is read using the voltage drop across the low side mosfets R

dsON

across a sense resistor (R

SENSE

) and internally converted into a current. The Tran conductance ratio is issued

by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.
The full differential current reading rejects noise and allows to place sensing element in different locations with-
out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in
which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx
at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two
pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet R

dsON

sense is implemented to avoid absolute maximum rating overcome on ISENx pin).

The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and
negative current. This circuit reproduces the current flowing through the sensing element using a high speed
Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF
time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least
200ns to make proper reading of the delivered current

This circuit sources a constant 50

A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at

the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following
equation:

CH3 = HGATE1; CH4 = HGATE2

CH3 = LGATE1; CH4 = LGATE2

ISENx

SENSE

PHASE

----------------------------------------------

IN FO x

11/33

L6919E

Figure 4. Current Reading Timing (Left) and Circuit (Right)

Where R

SENSE

is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance

resistor used between ISENx and PGNDSx pins toward the reading points; I

PHASE

is the current carried by each

phase and, in particular, the current measured in the middle of the oscillator period

The current information reproduced internally is represented by the second term of the previous equation as
follow:

Since the current is read in differential mode, also negative current information is kept; this allow the device to
check for dangerous returning current between the two phases assuring the complete equalization between the
phase's currents. From the current information of each phase, information about the total current delivered (I

INFO1

INFO2

) and the average current for each phase (I

AVG

=(I

INFO1

INFO2

)/2 ) is taken. I

INFOX

is then com-

pared to I

AVG

to give the correction to the PWM output in order to equalize the current carried by the two phases.

The transconductance resistor Rg can be designed in order to have current information of 25

A per phase at

full nominal load; the over current intervention threshold is set at 140% of the nominal (I

INFOx

= 35

A). According

to the above relationship, the over current threshold (I

OCPx

) for each phase, which has to be placed at one half

of the total delivered maximum current, results:

Since the device senses the output current across the low-side mosfets (or across a sense resistors in series
with them) the device limits the bottom of the inductor current triangular waveform: an over current is detected
when the current flowing into the sense element is greater than I

OCPx

INFOx

> 35

A).

Introducing now the maximum ON time dependence with the delivered current (where T is the switching period
T=1/f

This linear dependence has a value at zero load of 0.80·T and at maximum current of 0.40·T typical and results
in two different behaviors of the device:

µ
µ
µ
µ

ISENx

LGATEX

ISENX

PGNDSX

LS1

LS2

Track & Hold

Total current
information

IN FO x

SENSE

PHASE

----------------------------------------------

O C Px

A Rg

S EN SE

---------------------------

OC P x

SE NSE

-------------------------------------------

O N ,MAX

0.80

5.73 k

(

)

0.80

SENSE

----------------------

O U T

5.73k

0.80 T I

F B

0.40 T I

F B

7 0

L6919E

12/33

1. T

Limited Output Voltage.

This happens when the maximum ON time is reached before the current in each phase reaches I

OCPx

INFOx

< 35

A).

Figure 5a shows the maximum output voltage that the device is able to regulate considering the T

limitation

imposed by the previous relationship. If the desired output characteristic crosses the T

limited maximum output

voltage, the output resulting voltage will start to drop after crossing. In this case, the device doesn't perform con-
stant current limitation but only limits the maximum ON time following the previous relationship. The output volt-
age follows the resulting characteristic (dotted in Figure 5b) until UVP is detected or anyway until I

= 70

Figure 5. T

Limited Operation

2. Constant Current Operation

This happens when ON time limitation is reached after the current in each phase reaches I

OCPx

INFOx

>35

A).

The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read
becomes lower than I

OCPx

INFOx

< 35

A) skipping clock cycles. The high side mosfets can be turned ON with

a T

imposed by the control loop at the next available clock cycle and the device works in the usual way until

another OCP event is detected.
This means that the average current delivered can slightly increase also in Over Current condition since the cur-
rent ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach
the I

OCPx

bottom. The worst-case condition is when the ON time reaches its maximum value.

When this happens, the device works in Constant Current and the output voltage decrease as the load increase.
Crossing the UVP threshold causes the device to latch (FAULT pin is driven high).

Figure 6 shows this working condition

It can be observed that the peak current (Ipeak) is greater than the I

OCPx

but it can be determined as follow:

Where V

outMIN

is the minimum output voltage (VID-30% as follow).

The device works in Constant-Current, and the output voltage decreases as the load increase, until the output
voltage reaches the Under-Voltage threshold (V

outMIN

). When this threshold is crossed, all mosfets are turned

off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The
maximum average current during the Constant-Current behavior results:

a) Maximum output Voltage

b) T

Limited Output Voltage

0.80·V

0.40·V

OUT

OCP

=2·I

OCPx

=70

Limited Output

characteristic

0.80·V

0.40·V

OUT

OCP

=2·I

OCPx

=70

Desired Output

characteristic and

UVP threshold

Resulting Output

characteristic

Ipea k

O C Px

Vo ut

M IN

---------------------------------------

T on

M AX

O C Px

Vo ut

M IN

---------------------------------------

0.40 T

M AX,TOT

2 I

MA X

O C Px

Ipe ak

OC P x

--------------------------------------

13/33

L6919E

Figure 6. Constant Current operation

In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed
(T

onMAX

) while the OFF time depends on the application:

Over current is set anyway when I

INFOx

reaches 35

A (I

= 70

A). The full load value is only a convention

to work with convenient values for I

. Since the OCP intervention threshold is fixed, to modify the percent-

age with respect to the load value, it can be simply considered that, for example, to have on OCP threshold
of 170%, this will correspond to I

INFOx

= 35

A (I

= 70

A). The full load current will then correspond to

INFOx

= 20.6

A (I

= 41.1

A).

Integrated Droop Function

The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing
the size and the cost of the output capacitor.

This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current

As shown in figure 7, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (V

DROOP

in figure 8) propor-

tional to the output current. Since the device has an average current mode regulation, the information about the
total current delivered is used to implement the Droop Function.

This current (equal to the sum of both I

INFOx

) is sourced from the FB pin. Connecting a resistor between this pin

and V

OUT

, the total current information flows only in this resistor because the compensation network between

FB and COMP has always a capacitor in series (See fig. 8). The voltage regulated is then equal to:

OUT

= V

- R

· I

Since I

depends on the current information about the two phases, the output characteristic vs. load current is

given by:

a) Maximum current for each phase

b) Output Characteristic

TonMAX

OCPx

Ipeak

MAX

Vout

Iout

=50

OCP

=2·I

OCPx

=70

MAX,TOT

UVP

Droop effect

O FF

Ipe ak

OC P x

O U T

--------------------------------------

ON m a x

O FF

------------------------------------------

O U T

VID

SENSE

----------------------

O U T

L6919E

14/33

Figure 7. Output transient response without (a) and with (b) the droop function

Figure 8. Active Droop Function Circuit

The feedback current is equal to 50

A at nominal full load (I

= I

INFO1

+ I

INFO2

) and 70

A at the OC intervention

threshold, so the maximum output voltage deviation is equal to:

FULL_POSITIVE_LOAD

= -R

· 50

OC_INTERVENTION

= -R

· 70

Droop function is provided only for positive load; if negative load is applied, and then I

INFOx

< 0, no current is

sunk from the FB pin. The device regulates at the voltage programmed by the VID.

REMOTE VOLTAGE SENSE

A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the re-
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR
is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power
plane results in common mode coupling for any picked-up noise.

If remote sense is not required, it is enough connecting RFB directly to the regulated voltage: VSEN becomes
not connected and still senses the output voltage through the remote buffer. In this case the FBG and FBR pins
must be connected anyway to the regulated voltage (See figure 10).

The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy on the output voltage
when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB
offset worsening the device performances.

MAX

MIN

NOM

(a)

(b)

ESR DROP

DROOP

Ref

COMP

To V

O UT

Total Current Info (I

INFO1

INFO2

)

DR OOP

Ref

COMP

To V

O UT

Total Current Info (I

INFO1

INFO2

)

DR OOP

15/33

L6919E

Figure 9. - Remote Buffer Connections

OUTPUT VOLTAGE MONITOR AND PROTECTIONS

The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage
the OVP / UVP conditions.

Power good output is forced low if the voltage sensed by VSEN is not within ±12% (Typ.) of the programmed
value. It is an open drain output and it is enabled only after the soft start is finished (2048 clock cycles after start-
up). During Soft-Start this pin is forced low.

Under voltage protection is provided. If the output voltage monitored by VSEN drops below the 60% of the ref-
erence voltage for more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven
high (5V). The condition is latched, to recover it is required to cycle the power supply.

Over Voltage protection is also provided: when the voltage monitored by VSEN reaches the OVP threshold
VOVP the controller permanently switches on both the low-side mosfets and switches off both the high-side
mosfets in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply (Vcc) turn off
and on is required to restart operations.

The over voltage percentage is then set by the ratio between the fixed OVP threshold VOVP and the reference
programmed by VID:

Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than the output volt-
age reaches 0.6V). The reference used in this case to determine the UV thresholds is the increasing voltage
driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference
programmed by the VID pins.

SOFT START AND INHIBIT

At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 10.

Once the soft start begins, the reference is increased: upper and lower MOS begin to switch and the output volt-
age starts to increase with closed loop regulation. At the end of the digital soft start, the Power Good comparator
is enabled and the PGOOD signal is then driven high (See fig. 10). The Under Voltage comparator is enabled
when the reference voltage reaches 0.6V. The Soft-Start will not take place, if both VCC and VCCDR pins are
not above their own turn-on thresholds.

During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.
Forcing the OSC/INH pin to a voltage lower than 0.6V (Typ.) disables the device: all the power mosfets and
protections are turned off until the condition is removed.

Reference

REMOTE

BUFFER

ERROR

AMPLIFIER

COMP

VSEN

FBG

FBR

Remote

Ground

Remote

OUT

64k

Reference

REMOTE

BUFFER

ERROR

AMPLIFIER

COMP

VSEN

FBG

FBR

64k

OUT

RB used (±0.5% Accuracy)

RB Not Used

O VP %

[ ]

O VP

Re feren ceVo ltage VID

(

)

-----------------------------------------------------------------------

100

L6919E

16/33

Figure 10. Soft Start

INPUT CAPACITOR

The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as
reported in figure 11. Considering the dual-phase topology, the input RMS current is highly reduced comparing
with a single phase operation.

Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships

It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst
case condition that happens for D = 0.25 and D = 0.75.

The power dissipated by the input capacitance is then equal to:

Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high RMS value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of
the single capacitor's RMS current.

Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible

Timing Diagram

Acquisition:

(CH1=LGATEx; CH2=VCC; CH3=VOUT;

CCDR

LGATEx

PGOOD

OUT

Turn ON threshold

2048 Clock Cycles

0.50 0.75

0.25

0.50

0.25

Single Phase

Dual Phase

Duty Cycle (V

OUT

)

t

No

l
i
z

)

0.5

(2D

OUT

rms

R M S

ESR

R M S

(

)

17/33

L6919E

to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high
frequency noise decoupling, noise generated by parasitic components along power path.

OUTPUT CAPACITOR

Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/

s, the output capacitor is a basic component for the fast response of the power supply.

Dual phase topology reduces the amount of output capacitance needed because of faster load transient response
(switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift
between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple.

When a load transient is applied to the converter's output, for first few microseconds the current to the load is sup-
plied by the output capacitors. The controller recognizes immediately the load transient and increases the duty
cycle, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):

OUT

· ESR

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:

Where D

MAX

is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load

transient and the lower is the output voltage static ripple.

INDUCTOR DESIGN

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current

between 20% and 30% of the maximum output current. The inductance value can be cal-

culated with this relationship:

Where f

is the switching frequency, V

is the input voltage and V

OUT

is the output voltage.

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.

The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for

I load transient in case of enough fast compensation network response:

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.

O U T

4 C

O U T

MAX

O U T

(

)

-----------------------------------------------------------------------------------

O U T

S W

------------------------------

OU T

---------------

a pplic atio n

O U T

------------------------------

rem ov al

O U T

---------------

L6919E

18/33

Figure 12. Inductor ripple current vs V

OUT

MAIN CONTROL LOOP

The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop.
Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation:
the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control
loop fixes the output voltage equal to the reference programmed by VID. Figure 13 reports the block diagram of
the main control loop.

Figure 13. Main Control Loop Diagram

Current Sharing (CS) Control Loop

Active current sharing is implemented using the information from Tran conductance differential amplifier in an
average current mode control scheme. A current reference equal to the average of the read current (I

AVG

) is in-

ternally built; the error between the read current and this reference is converted to a voltage with a proper gain
and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 14).

The current sharing control is a high bandwidth control loop allowing current sharing even during load transients.

The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is

0.5

1.5

2.5

3.5

Output Voltage [V]

I
n

or R

i
p

l
e

[
A

]

L=3

Vin=12V

L=2

Vin=12V

L=1.5

H, Vin=12V

L=2

Vin=5V

L=1.5

Vin=5V

L=3

H, Vin=5V

PWM1

1/5

INFO2

INFO1

4/5

F(S)

PWM2

COMP

ERROR

AMPLIFIER

REFERENCE

PROGRAMMED

BY VID

CURRENT

SHARING

DUTY CYCLE

CORRECTION

D02IN1392

19/33

L6919E

necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran
conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the cur-
rent reading error is given by the following equation:

Where

READ

is the difference between one phase current and the ideal current (I

MAX

/2).

For R

SENSE

= 4m

and I

MAX

= 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and

Rsense mismatches.

Figure 14. Current Sharing Control Loop

Average Current Mode (ACM) Control Loop

The average current mode control loop is reported in figure 15. The current information I

sourced by the FB

pin flows into RFB implementing the dependence of the output voltage from the read current.

The ACM control loop gain results (obtained opening the loop after the COMP pin):

Where:

is the equivalent output resistance determined by the droop function;

(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied

load Ro;

(s) is the compensation network impedance;

(s) is the parallel of the two inductor impedance;

A(s) is the error amplifier gain;

· is the ACM PWM transfer function where

OSC

is the oscillator ramp amplitude

and has a typical value of 3V

Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop
gain results:

R E A D

M AX

--------------------

2m V

SENSE

M AX

----------------------------------------

PWM1

1/5

INFO2

INFO1

PWM2

COMP

OUT

CURRENT

SHARING

DUTY CYCLE

CORRECTION

D02IN1393

LO O P

( )

PWM Z

( )

D R O O P

( )

(

)

( )

(

)

( )

A s

( )

---------------

A s

( )

------------

--------------------------------------------------------------------------------------------------------------------

D R OO P

s en se

-------------------

PWM

4
5

---

O SC

-------------------

L6919E

20/33

With further simplifications, it results:

Considering now that in the application of interest it can be assumed that Ro>>R

; ESR<<Ro and

DROOP

<<Ro, it results:

The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes
with a constant -20dB/dec slope with the desired crossover frequency

. Neglecting the effect of Z

(s), the

transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the
zero is fixed by ESR and the Droop resistance.

To obtain the desired shape an R

-C

series network is considered for the Z

(s) implementation. A zero at

=1/R

is then introduced together with an integrator. This integrator minimizes the static error while placing

the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is assured (See Figure
15). In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower
than the above reported zero.Compensation network can be simply designed placing

and imposing

the cross-over frequency

as desired obtaining:

Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)

LAYOUT GUIDELINES

Since the device manages control functions and high-current drivers, layout is one of the most important things

LO O P

( )

4
5

---

OS C

-------------------

( )

------------------------------------

Rs
Rg

--------

( )

---------------

L OO P

( )

4
5

---

O SC

-------------------

( )

---------------

R o

D R O OP

R o

-------

--------------------------------------

s Co

D R O O P

//Ro

ESR

(

)

C o

L
2

---

2 R o

---------------

Co ESR

-------

----------------------------------------------------------------------------------------------------------------------------------

L OO P

( )

4
5

---

O SC

-------------------

( )

---------------

s Co

D R O O P

ESR

(

)

L
2

---

2 Ro

---------------

C o ESR

C o

-------

----------------------------------------------------------------------------------------------------------------------------------

O SC

----------------------------------

5
4

---

D R O O P

ESR

(

)

--------------------------------------------------------

C o

L
2

---

--------------------

Rout

Cout

ESR

L/2

REF

PWM

COMP

OUT

·
·
·
·

LOOP

(s)

4
5

---

I N

o sc

---------------

----------

21/33

L6919E

to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-
ation and a proper connection between signal and power ground can optimize the performance of the control
loops.

Integrated power drivers reduce components count and interconnections between control functions and drivers,
reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-
rect implementation.

Power Connections.

These are the connections where switching and continuous current flows from the input supply towards the load.
The first priority when placing components has to be reserved to this power section, minimizing the length of
each connection as much as possible.

To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane
and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must
be located as close as possible, together and to the controller.

Considering that the "electrical" components reported in figure are composed by more than one "physical" com-
ponent, a ground plane or "star" grounding connection is suggested to minimize effects due to multiple connec-
tions.

Figure 16. Power connections and related connections layout guidelines (same for both phases)

Fig. 16a shows the details of the power connections involved and the current loops. The input capacitance (C

LOAD

gate

HGATEx

PHASEx

LGATEx

PGNDx

OUT

BOOTx

LOAD

BOOTx

PHASEx

VCC

SGND

OUT

VCC

a. PCB power and ground planes areas

b. PCB small signal components placement

L6919E

22/33

or at least a portion of the total capacitance needed, has to be placed close to the power section in order to
eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required.

Power Connections Related.

Fig.16b shows some small signal components placement, and how and where to mix signal and power ground
planes. The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay
times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so
minimized.

In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a conse-
quence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals. Even if
these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of insta-
bilities are introduced jeopardizing good system behavior. One important consequence is that the switching
losses for the high side mosfet are significantly increased.

For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the
GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig
17). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected
directly to the High Side mosfet Source pin to have a proper driving for this mosfet.

For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if
implemented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also
PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess
of 2A (30 mils wide is suggested).

Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system
efficiency.

Figure 17. Device orientation (left) and sense nets routing (right)

The placement of other components is also important:

The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini-

mize the loop that is created.

Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.

Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor

sustains the peak currents requested by the low-side mosfet drivers.

Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also

the optional resistor from FB to GND used to give the positive droop effect.

Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect

and to ensure the right precision to the regulation when the remote sense buffer is not used.

Towards HS mosfet

(30 mils wide)

Towards LS mosfet

(30 mils wide)

Towards HS mosfet

(30 mils wide)

To LS mosfet

(or sense resistor)

To regulated output

To LS mosfet

(or sense resistor)

23/33

L6919E

An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reduc-

ing noise.

PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed

on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device
can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the
use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the
low side mosfets, to a value lower than 26V, for 20nSec, at FSW of 600kHz max.

Current Sense Connections.

Remote Buffer: The input connections for this components must be routed as parallel nets from the FBG/FBR
pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of
any common mode noise. Connecting these pins in points far from the load, will cause a non-optimum load reg-
ulation, increasing output tolerance.

Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in
order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point
must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important
to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible
to the sensing elements, dedicated current sense resistor or low side mosfet R

dsON

Moreover, when using the low side mosfet R

dsON

as current sense element, the ISENx pin is practically con-

nected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE!
The device won't work properly because of the noise generated by the return of the high side driver. In this case
route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide
net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is
always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In
this case the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net).

Right and wrong connections are reported in Figure 18.

Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter.

Figure 18. PCB layout connections for sense nets

Wrong (left) and correct (right) connections for the current reading sensing nets.

NOT CORRECT

CORRECT

To PHASE
connection

VIA to GND plane

To HS Gate
and Source

To LS Drain
and Source

L6919E

24/33

Demo Board Description

The L6919E demo board shows the operation of the device in a dual phase application. This evaluation board
allows output voltage adjustability (0.800V - 1.550V) through the switches S0-S4 and high output current capa-
bility.

The board has been laid out with the possibility to use up to two D

PACK mosfets for the low side switch in order

to give maximum flexibility in the mosfet choice.

The four layers demo board's copper thickness is of 70

m in order to minimize conduction losses considering

the high current that the circuit is able to deliver.

Demo board schematic circuit is reported in Figure 19.

Figure 19. Demo Board Schematic

Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the
remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output
voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR
connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers
JP3, JP4 and JP5. Local sense through the R7 is used for the regulation.

The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also
the mosfet driver supply voltage. Anyway, power conversion starts from V

and the device is supplied from V

(See Figure 20).

Figure 20. Power supply configuration

PGOOD

PGND

PGNDS2

ISEN2

LGATE2

VSEN

PHASE2

UGATE2

BOOT2

VCC

COMP

SGND

OSC / INH

VID0

VID1

VID2

VID3

VID4

PGNDS1

ISEN1

LGATE1

PHASE1

UGATE1

BOOT1

VCCDR

FBR

FBG

R11

C11..C13

C14,

C23

JP3

Vin

GNDin

GNDCORE

VoutCORE

PGOOD

FBG

FBR

L6919E

DZ1

JP2

JP1

R13

R15

R12

R14

C9,C10

R18

R17

R16

Q1a

Q3a

R19

R20

JP5

JP4

Vcc

GNDcc

JP6

To pin

VCC

R21

R10

C24

Vin

GNDin

DZ1

JP2

JP1

Vcc

GNDcc

JP6

To Vcc pin

To HS Drains (Power Input)

To BOOTx (HS Driver Supply)

To VCCDR pin (LS Driver Supply)

25/33

L6919E

Two main configurations can be distinguished: Single Supply (VCC=VIN=12V) and Double Supply (VCC=12V
VIN=5V or different).

Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail

that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to
supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the
HS driver is supplied with V

-V

DZ1

through BOOTx and JP2 must be shorted to the left to use V

or to

the right to use V

-V

DZ1

to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted

and JP2 can be freely shorted in one of the two positions.

Double Supply: In this case VCC supply directly the controller (12V) while V

supplies the HS drains

for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses
allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed
through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now V

or V

depending

on the requirements.

Some examples are reported in the following Figures 21 and 22.

Figure 21. Jumpers configuration: Double Supply

Figure 22. Jumpers configuration: Single Supply

Vin = 5V

GNDin

DZ1

JP2

JP1

Vcc = 12V

GNDcc

JP6

Vcc = 12V

HS Drains = 5V

HS Supply = 5V

VCCDR (LS Supply) = 5V

Vin = 5V

GNDin

DZ1

JP2

JP1

Vcc = 12V

GNDcc

JP6

Vcc = 12V

HS Drains = 5V

HS Supply = 12V

VCCDR (LS Supply) = 12V

(a) V

= 12V; V

BOOTx

= VCCDR = V

= 5V

(b) V

= V

BOOTx

= VCCDR = 12V; V

= 5V

Vin = 12V

GNDin

DZ1 6.8V

JP2

JP1

Vcc = Open

GNDcc

JP6

Vcc = 12V

HS Drains = 12V

HS Supply = 5.2V

VCCDR (LS Supply) = 12V

Vin = 12V

GNDin

DZ1

JP2

JP1

Vcc = Open

GNDcc

JP6

Vcc = 12V

HS Drains = 12V

HS Supply = 12V

VCCDR (LS Supply) = 12V

(a) V

= V

= VCCDR = 12V; V

BOOTx

= 5.2V

(b) V

= V

BOOTx

= VCCDR = 12V

27/33

L6919E

CPU Power Supply: 5 to 12V

; 1.2V

OUT

; 45A

Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast
reaction, this helps in reducing output and input capacitor. Inductance value is also reduced.

A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen-
sation network. Considering the high output current, power conversion will start from the 12V bus.

Current Reading Network and Over Current:

Since the maximum output current is I

MAX

= 45A, the over current threshold has been set to 45A (22.5A

x 2)in the worst case (max mosfet temperature). Since the device limits the valley of the triangular ripple
across the inductors, the current ripple must be considered too. Considering the inductor core satura-
tion, a current ripple of 10A has to be considered so that the OCP threshold in worst case becomes
OCPx=17A (22.5A-5A). Considering to sense the output current across the low-side mosfet RdsON,
SUB85N03L-04P has 4.3m

max at 25°C that becomes 5.6m

at 100ºC considering the temperature

variation; the resulting transconductance resistor Rg has to be:

Droop function Design:

Considering a voltage drop of 70mV at full load, the feedback resistor R

has to be:

Inductor design:

Transient response performance needs a compromise in the inductor choice value: the biggest the in-
ductor, the highest the efficient but the worse the transient response and vice versa.
Considering then an inductor value of 0.8

H, the current ripple becomes:

Output Capacitor:

Five Rubycon MBZ (2200

F / 6.3V / 12m

max ESR) has been used implementing a resulting ESR of

2.4m

resulting in an ESR voltage drop of 45A · 2.4m

= 108mV after a 45A load transient.

Compensation Network:

A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient.
The R

network results:

(R8)

(C2)

Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic
components.

O C Px

d sO N

------------------

5.6m

-------------

2.7k

(R3 to R6)

70mV

----------------

(R7)

Vin

Vout

-----------------------------

Fsw

-----------

1.2

0.8

---------------------

1.2

--------

200k

-------------

6.5A (L1, L2)

F B

O S

------------------------------

5
4

---

D R OOP

ESR

(

)

-------------------------------------------------------

1K 2

---------------

5
4

---

20K 2

0.8

5.6m

2.7

-------------

1.2k

2.4m

---------------------------------------------------------------

2.0k

C o

L
2

---

--------------------

6 2200

-------

-----------------------------------------

33nF

L6919E

28/33

Part List
R2

147k

SMD 0805

R1, R20,R21

Not Mounted

SMD 0805

R3, R4, R5, R6

2.7k

SMD 0805

1.8k

SMD 0805

47k

SMD 0805

R10

510

SMD 0805

R11

SMD 0805

R12 to R19

SMD 0805

Not Mounted

SMD 0805

22n

SMD 0805

C3, C4

100n

SMD 0805

C5, C6, C7, C8

Ceramic

SMD 1206

C9, C10

or 22

/ 16V

TDK Multilayer Ceramic SMD 1206

C11 to C13

1800

/ 16V

Rubycon MBZ

Radial 10x23

C14 to C18

2200

/ 6.3V

Rubycon MBZ

Radial 10x20

C24

100n

SMD 0805

L1, L2

0.8

77121 - 4Turns

L6919E

STMicroelectronics

SO28

Q1, Q3

SUB85N03-04P

Vishay

PACK

Q2, Q4

SUB70N03-09BP

Vishay

PACK

D1, D2

STPS340U

STMicroelectronics

SMB

D3, D4

1N4148

STMicroelectronics

SOT23

S0,S4

Short

S1,S2,S3

Open

STATIC PERFORMANCES

Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without air-
flow at ambient temperature.

Figure 24. System Efficiency

Output Current [A]

f
i
ci

cy [

]

29/33

L6919E

Figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow
or heat sink. It can be observed that the mosfets are under 100ºC in any conditions. Load regulation is also re-
ported from 10A to 45A.

Figure 25. Mosfet Temperature and Load Regulation

DYNAMIC PERFORMANCES

Figure 26 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the
±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR.

Figure 26. 3A to 45A Load Transient Response

Figure 27 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A).

Figure 27. Dynamic VID Response

100

Output Current [A]

atu

r
e

[

High-side MOS Q2

High-side MOS Q4

Low -side MOS Q1

Low -side MOS Q3

1.170

1.180

1.190

1.200

1.210

1.220

1.230

1.240

1.250

Output Current [A]

out

[

]

L6919E

30/33

DEMO BOARD ENHANCEMENTS: 1.200V / 52A CPU Power Supply

Considering the same application schematic, minor changes can be done to achieve the 52A thermal output
current required by AMD Hammer processor core. Part list has been modified as follow:

Part List
R2

147k

SMD 0806

R1, R20,R21

Not Mounted

SMD 0805

R3, R4, R5, R6

1.5k

SMD 0805

1.8k

SMD 0805

47k

SMD 0805

R10

510

SMD 0805

R11

SMD 0805

R12 to R19

SMD 0805

Not Mounted

SMD 0805

10n

SMD 0805

C3, C4

100n

SMD 0805

C5, C6, C7, C8

Ceramic

SMD 1206

C9, C10

or 22

/ 16V

TDK Multilayer Ceramic SMD 1206

C11 to C13

1800

/ 16V

Rubycon MBZ

Radial 10x23

C14 to C18

2200

/ 6.3V

Rubycon MBZ

Radial 10x20

C24

100n

SMD 0805

L1, L2

0.8

77121 - 4Turns

L6919E

STMicroelectronics

SO28

Q1, Q1a, Q3, Q3a

SUB85N03-04P

Vishay-Siliconix

PACK

Q2, Q4

SUB70N03-09BP

Vishay-Siliconix

PACK

D1, D2

STPS340U

STMicroelectronics

SMB

D3, D4

1N4148

STMicroelectronics

SOT23

S0,S4

Short

S1,S2,S3

Open

STATIC PERFORMANCES

Figure 28 shows the demo board measured efficiency versus load current in steady state conditions without air-
flow at ambient temperature.

Figure 28. System Efficiency

Output Current [A]

f
f
i
ci

cy [

]

31/33

L6919E

Figure 29 shows the mosfets temperature versus output current in steady state condition without any air-flow
or heat sink. It can be observed that the mosfets are under 105°C in any conditions. Load regulation is also re-
ported from 10A to 55A.

Figure 29. Mosfet Temperature and Load Regulation.

Figure 30 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the
±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR.

Figure 30. 3A to 45A Load Transient Response

Figure 31 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A).

Figure 31. Dynamic VID Response

105

115

10 15 20 25 30 35 40 45 50 55 60

Output Current [A]

S T

r
e [

High-side M OS Q2

High-side M OS Q4

Lo w-side M OS Q1

Lo w-side M OS Q3

1.155

1.165

1.175

1.185

1.195

1.205

1.215

1.225

1.235

5 10 15 20 25 30 35 40 45 50 55 60

Output Current [A]

out

[

]

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

www.st.com

33/33

L6919E

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L6919E

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L6919E