1/23
L6997
April 2003
FEATURES
s
FROM 3V TO 5.5V V
CC
RANGE.
s
MINIMUM OUTPUT VOLTAGE AS LOW AS
0.6V.
s
1V TO 28V INPUT VOLTAGE RANGE.
s
CONSTANT ON TIME TOPOLOGY ALLOWS.
OPERATION WITH VERYLOW AND HIGH
DUTY CYCLES.
s
VERY FAST LOAD TRANSIENTS.
s
0.6V, 1% VREF.
s
SELECTABLE SINKING MODE.
s
LOSSLESS CURRENT LIMIT, AVAILABLE
ALSO IN SINKING MODE
s
REMOTE SENSING.
s
OVP,UVP LATCHED PROTECTIONS.
s
600
A TYP QUIESCENT CURRENT.
s
POWER GOOD AND OVP SIGNALS.
s
PULSE SKIPPING AT LIGTH LOADS.
s
94% EFFICIENCY FROM 3.3V TO 2.5V.
APPLICATIONS
s
NETWORKING.
s
DC/DC MODULES.
s
DISTRIBUTED POWER.
s
MOBILE APPLICATIONS.
s
CHIP SET, CPU, DSP AND MEMORIES SUPPLY.
DESCRIPTION
The device is a high efficient solution for networking
dc/dc modules and mobile application compatible
with 3.3V bus and 5V bus.
It's able to regulate an output voltage as low as 0.6V.
The constant on time topology assures fast load tran-
sient response. The embedded voltage feed-forward
provides nearly constant switching frequency opera-
tion.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The remote sensing improves the static and dynamic
regulation, recovering the wires voltage drop.
Pulse skipping technique reduces power consump-
tion at light loads. Drivers current capability allows
output currents in excess of 20A.
TSSOP20
ORDERING NUMBERS: L6997D
L6997DTR
STEP DOWN CONTROLLER
FOR LOW VOLTAGE OPERATIONS
MINIMUM COMPONENT COUNT APPLICATION
L6997
SHDN
3.3V
INT
VDR
VSENSE
OVP
Vref
GND
GNDSENSE
VFB
VCC
SS
OSC
0.6V
PGOOD
PGND
LGATE
PHASE
HGATE
ILIM
BOOT
Rilim
Css
Cvref
HS
LS
Rin1
Rin2
Cin
Cboot
Dboot
L
Cout
Ro1
Ro2
DS
L6997
2/23
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION (Top View)
Symbol
Parameter
Value
Unit
V
CC
V
CC
to GND
-0.3 to 6
V
V
DR
V
DR
to GND
-0.3 to 6
V
HGATE and BOOT, to PHASE
-0.3 to 6
V
HGATE and BOOT, to PGND
-0.3 to 36
V
V
PHASE
PHASE
-0.3-to 30
V
LGATE to PGND
-0.3 to V
DR
+0.3
V
ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF, INT,
GND
SENSE
to GND
-0.3 to V
CC
+0.3
V
P
tot
Power dissipation at T
amb
= 25C
1
W
T
stg
Storage temperature range
-40 to 150
C
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
125
C/W
T
j
Junction operating temperature range
-40 to 125
C
PIN FUNCTION
N
Name
Description
1
NOSKIP
Connect to V
CC
to force continuous conduction mode and sink mode.
2
GNDSE
NSE
Remote ground sensing pin
3
INT
Integrator output. Short this pin to VFB pin and connect it via a capacitor to V
OUT
to insert the
integrator in the control loop. If the integrator is not used, short this pin to VREF.
4
VSENS
E
This pin must be connected to the remote output voltage to detect overvoltage and undervoltage
conditions and to provide integrator feedback input.
5
V
CC
IC Supply Voltage.
6
GND
Signal ground
7
VREF
0.6V voltage reference. Connect max. a 10nF ceramic capacitor between this pin and ground.
This pin is capable to source or sink up to 250uA
GNDSENSE
INT
OVP
SHDN
ILIM
OSC
VCC
NOSKIP
PGOOD
LGATE
PGND
VDR
PHASE
HGATE
BOOT
1
3
2
4
5
6
7
8
9
18
17
16
15
14
13
19
20
10
SS
GND
11
12
VREF
VFB
TSSOP20
INT
VSENSE
3/23
L6997
8
VFB
PWM comparator feedback input. Short this pin to INT pin when using the integrator function, or
to VSENSE pin without integrator.
9
OSC
Connect this pin to the input voltage through a voltage divider in order to provide the feed-
forward function. It cannot be left floating.
10
SS
Soft start pin. A 5
A constant current charges an external capacitor which value sets the soft-
start time.
11
ILIM
An external resistor connected between this pin and GND sets the current limit threshold.
12
SHDN
Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating.
13
OVP
Open drain output. During the over voltage condition it is pulled up by an external resistor.
14
PGOOD
Open drain output. During the soft start and in case of output voltage fault it is low. It is pulled up
by external resistor.
15
PGND
Low Side driver ground.
16
LGATE
Low Side driver output.
17
V
DR
Low Side driver supply.
18
PHASE
Return path of the High Side driver.
19
HGATE
High side MOSFETS driver output.
20
BOOT
Bootstrap capacitor pin. High Side driver is supplied through this pin.
ELECTRICAL CHARACTERISTICS
(V
CC
= V
DR
= 3.3V; T
amb
= 0C to 85C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY SECTION
Vin
Input voltage range
Vout=Vref Fsw=110Khz Iout=1A
1
28
V
V
CC
,
V
DR
3
5.5
V
V
CC
Turn-onvoltage
2.86
2.97
V
Turn-off voltage
2.75
2.9
V
Hysteresis
90
mV
IqV
DR
Quiescent Current Drivers
VFB > VREF
7
20
A
IqVcc
Device Quiescent current
VFB > VREF
400
600
A
SHUTDOWN SECTION
SHDN
Device On
1.2
V
Device Off
0.6
V
I
SH
V
DR
Drivers shutdown current
SHDN to GND
5
A
I
SH
V
CC
Devices shutdown current
SHDN to GND
1
15
A
SOFT START SECTION
I
SS
Soft Start current
V
SS
= 0.4V
4
6
A
Active Soft start and voltage
300
400
500
mV
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
ILIM input bias current
R
ILIM
= 2K
to 200K
4.6
5
5.4
A
Zero Crossing Comparator offset
Phase-gnd
-2
2
mV
DK
ILIM
Current limit factor
1.6
1.8
2
A
PIN FUNCTION (continued)
N
Name
Description
L6997
4/23
ON TIME
Ton
On time duration
V
REF
=V
SENSE OSC
=125mV
720
800
880
ns
V
REF
=V
SENSE OSC
=250mV
370
420
470
ns
V
REF
=V
SENSE OSC
=500mV
210
240
270
ns
OFF TIME
T
OFFMIN
Minimum off time
600
ns
K
OSC
/T
OFFMIN
OSC=250mV
0.3
0.33
VOLTAGE REFERENCE
VREF
Voltage Accuracy
0
A < I
REF
< 100
A
0.594
0.6
0.606
V
PWM COMPARATOR
Input voltage offset
-2
+2
mV
I
FB
Input Bias Current
20
nA
INTEGRATOR
INT
Over Voltage Clamp
V
SENSE
= V
CC
0.62
0.75
0.88
V
INT
Under Voltage Clamp
V
SENSE
= GND
0.45
0.55
0.65
V
Integrator Input Offset Voltage
V
SENSE
-V
REF
-4
-4
mV
I
VSENSE
Input Bias Current
20
nA
GATE DRIVERS
High side rise time
V
DR
=3.3V; C=7nF
HGATE - PHASE from 1 to 3V
50
90
ns
High side fall time
50
100
ns
Low side rise time
V
DR
=3.3V; C=14nF
LGATE from 1 to 3V
50
90
ns
Low side fall time
50
90
ns
P
GOOD
UVP/OVP PROTECTIONS
OVP
Over voltage threshold
with respect to V
REF
118
121
124
%
UVP
Under voltage threshold
67
70
73
%
PGOOD
Upper threshold
(V
SENSE
-V
REF
)
V
SENSE
rising
110
112
116
%
PGOOD
Lower threshold
(V
SENSE
-V
REF
)
V
SENSE
falling
85
88
91
%
V
PGOOD
I
Sink
=2mA
0.2
0.4
V
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= V
DR
= 3.3V; T
amb
= 0C to 85C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
5/23
L6997
Figure 1. Functional & Block Diagram
+
+
-
PHASE
SENSEGND
Gm
VSENSE
VSENSE
VSENSE
VSENSE
-
-
NOSKIP
0.6V
Ref
erence chain
INT
V
+
-
V
-
+
dela
y
T
off min
IN
IN
-
PHASE
VSENSE
VREF
+
-
+
-
+
+
1.416
1.236V
bandgap
+
mode
no-skip
no-skip
OSC
LS control
VREF
VREF
pwm compar
ator
FB
-
+
VREF
compar
ator
positiv
e current limit
VSENSE
PGND
LGA
TE
VDR
PHASE
HGA
TE
BOO
T
GND
VCC
OV
P
PGOOD
SHDN
SS
ILIM
OSC
compar
ator
negativ
e current limit
LS and HS anti-cross-conduction compar
ators
comp
V(LGA
TE)<0.5V
comp
V(PHASE)<0.2V
HS control
0.05
ILIM
0.05
o
v
er
v
oltage compar
ator
under
v
oltage compar
ator
-
+
-
IC enab
le
SR
1.12 VREF
control
soft-star
t
po
w
er management
pgood compar
ators
0.925 VREF
1.075 VREF
-
+
0.6 VREF
5 uA
le
v
el shifter
VCC
z
ero-cross compar
ator
one-shot
one-shot
T
on min
To
n
T
on= K
osc
V(VSENSE)/V(OSC)
VSENSE
mode
PHASE
HS dr
iv
er
LS dr
iv
er
To
n
Vcc
V
one-shot
OSC
T
on= K
osc
V(VSENSE)/V(OSC)
OUT
S
R
Q
R
S
Q
R
S
Q
L6997
6/23
1
DEVICE DESCRIPTION
1.1 Constant On Time PWM topology
Figure 2. Loop block schematic diagram
The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time
duration forced by the one-shot generator. The on time is directly proportional to VSENSE pin voltage and in-
verse to OSC pin voltage as in Eq1:
Eq 1
where K
OSC
= 250ns and
is the internal propagation delay time (typ. 70ns). The system imposes in steady
state a minimum on time corresponding to V
OSC
= 1V. In fact if the V
OSC
voltage increases above 1V the cor-
responding Ton will not decrease. Connecting the OSC pin to a voltage partition from V
IN
to GND, it allows a
steady-state switching frequency F
SW
independent of V
IN
. It results:
Eq 2
where
Eq 3
Eq 4
The above equations allow setting the frequency divider ratio
OSC
once output voltage has been set; note that
such equations hold only if V
OSC
<1V. Further the Eq2 shows how the system has a switching frequency ideally
independent from the input voltage. The delay introduces a light dependence from V
IN
. A minimum off-time con-
strain of about 500ns is introduced in order to assure the boot capacitor charge and to limit the switching fre-
Q
Vsense
R3
R4
R2
R1
R
S
Vout
Vin
HGATE
LGATE
Q
OSC
FB
Vref
HS
LS
DS
PWM comparator
FFSR
One-shot generator
-
+
T
O N
K
O SC
V
SENSE
V
O SC
----------------------
+
=
f
SW
V
O U T
V
IN
---------------
1
T
O N
-----------
O SC
O U T
---------------
1
K
O SC
---------------
O SC
f
SW
K
O SC
O U T
=
=
=
O SC
V
OS C
V
IN
---------------
R
2
R
2
R
1
+
--------------------
=
=
O U T
V
FB
V
O U T
---------------
R
4
R
3
R
4
+
--------------------
=
=
7/23
L6997
quency after a load transient as well as to mask PWM comparator output against noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage on the OSC pin must range between 50mV and 1V to ensure the system linearity.
1.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage
(0.6V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise
spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then
turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 1.
The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC
error. Further the system regulates the output voltage valley value not the average, as in the Figure 3 is shown.
So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate
the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to
the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 4. The internal integrator am-
plifier with the external capacitor C
INT1
introduces a DC pole in the control loop. C
INT1
also provides an AC path
for output ripple.
Figure 3. Valley regulation
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage
ranges from V
REF
-50mV, V
REF
+150mV. This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case of the ripple amplitude is larger than 150mV, a capacitor C
INT2
can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose
C
INT1
according to the following equation:
Eq 5
where GINT=50 s is the integrator transconductance,
OUT
is the output divider ratio given from Eq4 and F
U
is the close loop bandwidth. This equation also holds if C
INT2
is connected between INT pin and ground. C
INT2
is given by:
Time
Vout
Vref
<Vout>
DC Error Offset
C
IN T1
g
IN T
O U T
2
F
u
-------------------------------
=
L6997
8/23
Eq 6
Where
V
OUT
is the output ripple and
V
INT
is the ripple wanted at the INT pin (100mV typ).
Figure 4. Integrator loop block diagram
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hys-
teretic system the frequency can change with some parameters (input voltage, output current). In L6997 is im-
plemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate
operation with the input voltage variation. There are many factors affecting switching frequency accuracy in
steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver.
Others related to the external components as high side MOSFET gate charge and gate resistance, voltage
drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.
During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
1.3 Transition from PWM to PFM/PSK
To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turns-
on the low side MOSFET, until the inductor current reaches the zero A value, when the zero-crossing compar-
ator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground,
through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps
the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow
through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in
fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOS-
FET when the output voltage goes down a reference value. The device works in discontinuous mode at light
load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around
half the inductor current ripple. This threshold value depends on V
IN
, L, and V
OUT
. Note that the higher the in-
C
IN T 2
C
IN T 1
----------------
V
O U T
V
IN T
------------------
=
PCB TRACES
LOAD
From Vsense
Q
Cint1
R1
INT
Vref
FB
DS
R
S
Vout
Vin
HGATE
LGATE
Q
OSC
Vref
One-shot generator
FFSR
PWM comparator
Vsense
Gndsense
R2
Cint2
HS
LS
Integrator amplifier
+
-
-
+
+
-
9/23
L6997
ductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the
transient response is. In PFM mode the frequency changes, with the output current changing, more than in
PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive
turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and
asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM
is not compatible with the application it can be disabled connecting to V
CC
the NOSKIP pin.
1.4 Softstart
If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side
MOSFET and the low side MOSFET off (high impedance mode). After the SHDN pin is turned on the SS pin
voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the
current limit threshold to avoid output overvoltage. The active soft start range for the V
SS
voltage (where the
output current limit increase linearly) starts from 0.6V to 1V. In this range an internal current source (5
A Typ)
charges the capacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM
pin is proportional to SS pin voltage and it saturates at 5
A (Typ.) when SS voltage is close to 1V and the max-
imum current limit is active. Output protections OVP & UVP are disabled until the SS pin voltage reaches 1V
(see figure 5).
Once the SS pin voltage reaches the 1V value, the voltage on SS pin doesn't impact the system operation any-
more. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first turn-
on the power section and after the logic section (V
CC
pin).
Figure 5. Soft -Start Diagram
Because the system implements the soft start controlling the inductor current, the soft start capacitor selection
is function of the output capacitance, the current limit and the soft start active range (
V
SS
).
In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before
the soft start voltage reaches the under voltage value (1V). In other words the output voltage charging time has
to be lower than the uvp time.
The UVP time is given by:
Eq 7
In order to calculate the output volatge chargin time it should be calculated, before, the output volatrge function
versus time. This function can be calculated from the inductor current function; the inductor current function can
Time
Time
0.6V
Maximum current limit
Soft-start active range
5
A
4.1V
1V
Ilim current
Vss
T
uv p
C
SS
(
)
V
uv p
Iss
------------
C
SS
=
L6997
10/23
be supposed linear function of the time.
Eq 8
so the output voltage is given by:
Eq 9
calling V
out
as the V
out
final value, the output charging time can be estimated as:
Eq 10
the minimum C
SS
value is given imposing this condition:
Eq 11
T
out
=T
uvp
1.5 Current limit
The current limit comparator senses the inductor current through the low side MOSFET RDS
ON
drop and com-
pares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the one-shot start.
To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, V
IN
V
OUT
and switching frequency.
The average output current in current limit is given by:
Eq 12
Thus, to set the current threshold, choose RILIM according to the following equation:
Eq 13
In current limit the system keeps the current constant until the output voltage meets the undervolatge threshold.
The negative valley current limit, for the sink mode, is set automatically at the same value of the positive valley
current limit. The average negative current limit differs from the positive average current limit by the ripple cur-
rent; this difference is due to the valley control technique.
The system accuracy is function of the exactness of the resistance connected to ILIM pin and the low side MOS-
FET RDS
ON
accuracy. Moreover the voltage on ILIM pin must range between 10mV and 1V to ensure the sys-
tem linearity.
Figure 6. Current limit schematic
I
L
t,C
SS
(
)
R
ilim
/R
ds on
K
C
I
SS
t
(
)
V
SS
C
SS
(
)
-------------------------------------------------------------------
=
V
o ut
t,C
S S
(
)
Q t,C
SS
(
)
C
ou t
-------------------------
R
ilim
/R
ds on
K
C
I
S S
t
2
(
)
C
ou t
V
SS
C
SS
2
(
)
----------------------------------------------------------------------
=
=
I
out
C
SS
(
)
V
ou t
C
o ut
V
S S
C
SS
2
(
)
R
ilim
/R
dso n
K
C
I
SS
(
)
----------------------------------------------------------------------------
0.5
=
I
O U T
C L
I
m ax valley
I
2
-----
+
=
m ax valley
R
IL im
Rd s
o n
-----------------
K
ILIM
=
Positive and negative current limit
R
ILIM
5A
Current
Comparator
To
logic
PGN
D
PHASE
To inductor
LS
11/23
L6997
1.6 Protection and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of
the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low
side MOSFET and, high side MOSFET are turned off and PGOOD goes low. In case the system detects an
overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply
has to be removed, and restart with the correct sequence.
These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV
fault).
1.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the ex-
ternal power MOSFET gate charge and switching frequency.
Eq 14
The maximum gate charge values for the low side and high side are given from:
Eq 15
Eq 16
Where f
SW0
= 500Khz. The equations above are valid for T
J
= 150C. If the system temperature is lower the Q
G
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is Q
MAXLS
= 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
Because the driver voltage can be very low it should be considered also the ULTRA LOW VOLTAGE MOSFET.
This kind of MOSFET has very low threshold voltage, so the overdrive voltage can be enough to ensure correct
transition and low enough RDS
ON
.
P
drive r
V
cc
Q
g TO T
F
SW
=
Q
MAX H S
f
SW 0
f
SW
-------------
75n C
=
Q
MAX LS
f
SW0
f
SW
-------------
125 nC
=
L6997
12/23
2
APPLICATION INFORMATION
2.1 5A Demo board description
The demo board shows the device operation in this condition: VI
N
from 3.3V to 5V, I
OUT
=5A V
OUT
=1.25V. The
evaluation board let use the system with 2 different voltages (V
CC
the supply for the IC and V
IN
the power input
for the conversion) so replacing the input capacitors the power input voltage could be also 28V. When instead
the input voltage (V
IN
) is equal to the V
CC
it should be better joining them with a 10
resistor in order to filter the
device input voltage. On the topside demo there are two different jumpers: one jumper, near the OVP and POW-
ER GOOD test points, is used to shut down the device; when the jumper is present the device is in SHUTDOWN
mode, to run the device remove the jumper. The other jumper, near the V
REF
test point, is used to set the PFM/
PSK mode. When the jumper is present, at light load, the system will go in PFM mode; if there is not the jumper,
at light load, the system will remain in PWM mode. In the demo bottom side there are two others different jump-
ers. They are used to set or remove the INTEGRATOR configuration. When the jumpers named with INT label
are closed AND the jumpers named with the NOINT label are open the integrator configuration is set. Some-
times the integrator configuration needs a low frequency filter the to reduce the noise interaction. In this case
instead close the INT jumpers put there a resistor and after a capacitor to ground (as in the schematic diagram);
the pole value is around 500Khz but it should be higher enough than the switching frequency (ten times). On
the opposite when the jumpers named with the NOINT are closed and the jumpers named with INT are open
the NON INTEGRATOR configuration is selected. Refer to the Table 1 and 2 for the jumpers connection.
Figure 7. Demoboard Schematic Diagram
C14,C15
R3
R10
TP1
TP2
C10
R6
Q1
D2
TP3
C2
C6
R8
C12
C9
R9
R1
D1
R2
R5
SD
NS
L1
R7
C7,C13
C11
C4
R4
Rn
C3
C1
Q2
Cn
INT
INT
NOINT
NOINT
C5
C8
Vcc
SHDN
VREF
OSC
NOSKIP
VDR
INT
VFB
GNDSENSE
SS
BOOT
ILIM
HGATE
PHASE
LGATE
PGND
GND
VSENSE
OVP
PGOOD
VCC
VOUT
GNDOUT
GNDin
VIin
L6997
J1
13/23
L6997
2.2 Jumper Connection
Table 1. Jumper connection with integrator
* This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 2. Jumper connection without integrator
2.3 DEMOBOARD LAYOUT
Real dimensions: 4,7 cm X 2,7 cm (1.85 inch X 1. 063 inch)
Component
Connection
C1
Mounted
C2
Mounted *
INT
Close
NOINT
Open
Component
Connection
C1
Not mounted
C2
Not Mounted
INT
Open
NOINT
Close
Figure 8. Top side components placement
Figure 9. Bottom side Jumpers distribution
Figure 10. Top side layout
Figure 11. Bottom side layout
L6997
14/23
Table 3. PCB Layout guidelines
Table 4. Component list
The component list is shared in two sections: the first for the general-purpose component, the second for power
section:
GENERAL-PURPOSE SECTION
Goal
Suggestion
Low radiation and low magnetic coupling
with the adjacent circuitry.
1) Small switching current loop areas. (For example placing C
IN
, High
Side and Low side MOSFETS, Shottky diode as close as possible).
2) Controller placed as close as possible to the power MOSFET.
3) Group the gate drive component (Boot cap and diode together near
the IC.
Don't penalty the efficiency.
Keep power traces and load connections short and wide.
Ensure high accuracy in the current sense
system.
Phase pin and PGND pin must be made with Kelvin connection and as
close as possible to the Low Side MOSFETS.
Reduce the noise effect on IC.
1) Put the feedback component (like output divider, integrator network,
etc) as close as possible to the IC.
2) The feedback traces must be parallel and as close as possible.
Moreover they must be routed as far as possible from the switching
current loops..
Part name
Value
Dimension
Notes
RESISTOR
R1, R5, R9, R10
33k
0603
Pull-up resistor
R2
1k
0603
Output resistor divider
(To set output voltage)
R3
1.1k
0603
R4
0603
Input resistor divider
(To set switching frequency)
R6
470k
0603
R7
0
0603
R8
0603
Current limit resistor
CAPACITOR
C1
330pF
0603
First integrator capacitor
C2
N.M.
0603
Second integrator capacitor
C3
1nF
0603
C4
100nF
0603
C5
1
F
Tantalum
C6
10nF
0603
C9
10nF
0603
Softstart capacitor
C10
100nF
0603
C11
100nF
0603
C8, C12
47pF
0603
DIODE
D1
BAR18
15/23
L6997
POWER SECTION
Notes: 1. N.M.=Not Mounted
2. The demoboard with this component list is set to give: V
OUT
= 1.25V, F
SW
= 270kHz with an input voltage around V
IN
= V
CC
=
3.3V-5V and with the integrator feature.
3. The diode efficiency impact is very low; it is not a necessary component.
4. All capacitors are intended ceramic type otherwise specified.
2.4 EFFICIENCY CURVES
Source mode
V
IN
= 3.3V V
OUT
= 1.25V F
SW
= 270kHz
Figure 12. Efficiency vs output current
INPUT CAPACITORS
C7, C13
47
F
ECJ4XF0J476Z
PANASONIC
OUTPUT CAPACITORS
C14, C15
220
F
2R5TPE220M
POSCAP
INDUCTOR
L1
2.7
H
DO3316P-272HC
COILCRAFT
POWER MOS
Q1,Q2
STS5DNF20V
STMicroelectronics
Double mosfet in sigle package
DIODE
D2
STPS340U
STMicroelectronics
3
0,0
10,0
20,0
30,0
40,0
50,0
60,0
70,0
80,0
90,0
100,0
0,0
1,0
2,0
3,0
4,0
5,0
6,0
Current [A]
Eff [%]
PFM mode
PWM mode
L6997
16/23
3
STEP BY STEP DESIGN
V
IN
= 3.3V, 10% V
OUT
= 1.25V I
OUT
= 5A F
SW
= 270kHz
3.1 Input capacitor.
A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com-
ponent of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor:
Eq 17
The RMS current, which the capacitor must provide, is given by:
Eq 18
Neglecting the last term, the equation reduces to:
Eq 19
which maximum value corresponds to to
= 1/2.
ICIN
RMS
, has a maximum equal to
= 1/2 (@ VIN = 2VOUT, that is, 50% duty cycle). The input, therefore,
should be selected for a RMS ripple current rating as high as half the respective maximum output current.
Electrolytic capacitors are the most used cause are the cheapest ones and are available with a wide range of
RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically
larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small
size. The only problem is that they occasionally can burn if subjected to very high current during the charge. So,
it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high
surge current when connected to the power supply. If available for the requested value and voltage rating, the
ceramic capacitors have usually a higher RMS current rating for a given physical dimension (due to the very low
ESR). The drawback is the quite high cost. Possible solutions:
With our parameter from the equation 3 it is found:
Icin
rms
= 2.42A
3.2 Inductor
To define the inductor, it is necessary to determine firstly the inductance value. Its minimum value is given by:
Eq 20
where RF is given from
I/I
OUT
(basically it is around 30%).
10
F
C34Y5U1E106ZTE12 TOKIN
22
F
JMK325BJ226MM
TAIYO-YUDEN
47
F
ECJ4XF0J476Z
PANASONIC
33
F
C3225X5R0J476M
TDK
P
C IN
ESR
C IN
Iout
2
Vi n
Vi n
Vo ut
(
)
Vin
2
------------------------------------------------
=
Icin
rm s
Iout
2
1
(
)
12
------
I
L
(
)
2
+
=
Icin
rm s
Io ut
1
(
)
=
Lm i n
V
o
Vin
m ax
V
o
(
)
F
SW
I
out
RF Vin
m ax
---------------------------------------------------------------
17/23
L6997
With our parameters:
Lmin
2
H
The saturation current is around 5A
3.3 Output capacitor and ripple voltage
The output capacitor is chosen by the output voltage static precision and also dynamic precision. The static pre-
cision regards the output voltage ripple value rated the output voltage in steady state at the end the ESR value;
while the dynamic precision regards the load step positive and negative load transient.
If the static precision is around 1% for the 1.25V output voltage, the output precision is 12.5mV.
To determine the ESR value from the output precision is necessary to calculate the ripple current:
Eq 21
One can consider a switching frequency around 270kHz.
From the Eq. above the ripple current is around 1.25A.
So the ESR is given from: RMS current in output capacitor is given by:
Eq 22
The dynamic specifications are sometimes more relaxed than the static requirements, so one can consider the
ESR value around 20m
enough.
To allow the device control loop to properly work, output capacitor ESR zero must be at least ten times smaller
than switching frequency. Low ESR tantalum capacitors, which ESR zero is close to ten kHz, are suitable for
output filtering. Output capacitor value C
OUT
and its ESR, ESRC
OUT
, should be large enough and small enough,
respectively, to keep output voltage within the accuracy range during a load transient, and to give the device a
minimum signal to noise ratio.
The current ripple flows through the output capacitors, so the should be calculated also to sustain this ripple:
the RMS current value is given by Eq. 18.
Eq 23
But this is usually a negligible constrain.
Possible solutions:
3.4 MOSFET's and Schottky Diodes
Since a 3.3V bus powers the gate drivers of the device, the use ultra low level MOSFET is highly recommended,
especially for high current applications. The MOSFET breakdown voltage V
BRDSS
must be greater than VINMAX
with a certain margin, so the selection will address 20V or 30V devices (depends on applications).
The RDS
ON
can be selected once the allowable power dissipation has been established. By selecting identical
Power MOSFET as the main switch and the synchronous rectifier, the total power they dissipate does not de-
pend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required
RDS
ON
(@ 25 C) can be derived from:
330
F
EEFUE0D331R
PANASONIC
220
F
2R5TPE220M
POSCAP
I
Vi n
Vo
L
-----------------------
Vo
Vin
---------
T
s w
=
ESR
V
ripp le
I
2
-----
---------------------
25m V
1.25
----------------
=
20m
=
=
Icout
rms
1
2 3
-----------
I
L
=
L6997
18/23
Eq 24
is the temperature coefficient of RDS
ON
(typically,
= 510
-3
C
-1
for these low-voltage classes) and T the
admitted temperature rise. It is worth noticing, however, that generally the lower RDS
ON
, the higher is the gate
charge Q
G
, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q
G
moves
from the input source to ground, resulting in an equivalent drive current:
Eq 25
The SCHOTTKY diode to be placed in parallel to the synchronous rectifier must have a reverse voltage V
RRM
greater than VIN
MAX
; for low current application the SCHOTTKY is not necessary to increase the efficiency. In
order to use less space than possible, a double MOSFET in a single package is chosen: STS5DNF20V
3.5 Output voltage setting
The first step is choosing the output divider to set the output voltage. To select this value there isn't a criteria,
but a low divider network value (around 100
) decries the efficiency at low current; instead a high value divider
network (100K
) increase the noise effects. A network divider values from 1K
to 10K
is right. We chose:
R3 = 1K
R2 = 1.1K
The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum
output voltage is V
OUT
=VREF=0.6V. Once output divider and frequency divider have been designed as to obtain
the required output voltage and switching frequency, the following equation gives the smallest input voltage,
which allows L6997 to regulate (which corresponds to T
OFF
=T
OFFMIN
):
Eq 26
3.6 Voltage Feedforward
From the equations 1,2 3 choosing the switching frequency around 270kHz it can be selected the input divider.
For example:
R3 = 470K
R4 = 8.5K
3.7 Current limit resistor
From the equation 8 it can be set the valley current limit considering the STS5DNF20V Ultra logic Level Mosfet
with a current around 5A:
R8 = 120K
3.8 Integrator capacitor
Let it be F
U
= 15kHz, V
OUT
= 1.25V.
Since V
REF
= 0.6V, from equation 2, of the device description, it follows
O
UT
= 0.348 and, from equation 5 it
follows C = 250pF. The output ripple is around 22mV, so the system doesn't need the second integrator capac-
itor.
RDS
O N
P
O N
Io ut
2
1
T
+
(
)
-------------------------------------------------
=
Iq
Qg F
SW
=
1
OS C
O U T
---------------
1
K
O SC
T
OF F,M IN
--------------------------
MAX
----------------------------------------------
<
19/23
L6997
3.9 Soft start capacitor
Considering the soft start equations:
C
SS
= 150pF
The equations are valid without load. When an active load is present the equations result more complex; further
some active loads have unexpected effect, as higher current than the expected one during the soft start, can
change the start up time.
In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the
C
SS
value.
3.10 Sink mode
Figure 13. Efficiency vs output current
0,0
10,0
20,0
30,0
40,0
50,0
60,0
70,0
80,0
90,0
100,0
0,0
1,0
2,0
3,0
4,0
5,0
Current [A]
Eff [%]
L6997
20/23
4
TYPICAL OPERATING CHARACTERISTICS
Figure 14. Load transient response from 0A to 5A..
Figure 15. Normal functionality in SINK mode..
Figure 16. Normal functionality in PWM mode.
Figure 17. Normal functionality in PFM mode.
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
21/23
L6997
Figure 18. Start up waveform with 0A load.
Figure 19. Start up waveform with 5A load..
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
L6997
22/23
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.20
0.047
A1
0.050
0.150
0.002
0.006
A2
0.800
1.000
1.050
0.031
0.039
0.041
b
0.190
0.300
0.007
0.012
c
0.090
0.200
0.004
0.008
D (1)
6.400
6.500
6.600
0.252
0.256
0.260
E
6.200
6.400
6.600
0.244
0.252
0.260
E1 (1)
4.300
4.400
4.500
0.170
0.173
0.177
e
0.650
0.026
L
0.450
0.600
0.750
0.018
0.024
0.030
L1
1.000
0.039
k
0 (min.) 8 (max.)
aaa
0.100
0.004
Note:
1. D and E1 does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
TSSOP20
0087225 (Jedec MO-153-AC)
Thin Shrink Small Outline Package
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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23/23
L6997
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