1/21

L9347

June 2002

Quad low-side switch

2 x 5A designed as conventional switch

2 x 2.5A designed as switched current-regulator

Low ON-resistance 2 x 0.2

, 2 x 0.35

(typ.)

Power SO-36 - package with integrated
cooling area

Integrated free-wheeling and clamping Z-diodes

Output slope control

Short circuit protection

Selective overtemperature shutdown

Open load detection

Ground and supply loss detection

External clock control

Recirculation control

Regulator drift detection

Regulator error control

Regulator resolution 5mA

Status monitoring

Status push-pull stages

Electrostatic discharge (ESD) protection

DESCRIPTION

The L9347 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.

All channels are protected against fail functions.
They are monitored by a status output.

Figure 1. Pin Connection

N.C.

IN3

ST4

PGND3

33
32

PGND3

30
29

D3
D3

27
26

PGND2

24
23

VDD

VCC

21
20

IN2

ST1

GND

IN4

2
3

ST3

PGND4

5
6

Q4
Q4

8
9

11
12

PGND1

14
15

CLK

IN1

ST2

17
18

TEST

99AT0060

PowerSO-36

BARE

DIE

ORDERING NUMBERS:

L9347PD

L9347DIE1

INTELLIGENT QUAD (2

5A/2

2.5A) LOW-SIDE SWITCH

3/21

L9347

PIN DESCRIPTION

N�

Pin

Function

GND

Logic Ground

2, 3

PGND 3

Power Ground Channel 3

4, 5

Q 3

Power Output Channel 3

6, 7

D 3

Free-Wheeling Diode Channel 3

8, 9

Q 1

Power Output Channel 1

10, 11

Q 2

Power Output Channel 2

12, 13

D 4

Free-Wheeling Diode Channel 4

14, 15

Q 4

Power Output Channel 4

16, 17

PGND 4

Power Ground Channel 4

Not Connected

VCC

5V Supply

VDD

5V Supply

ST 4

Status Output Channel 4

IN 2

Control Input Channel 2

IN 4

Control Input Channel 4

ST 2

Status Output Channel 2

Enable Input for all four Channels

TEST

Enable Input for Drift detection

27, 28

PGND 2

Power Ground Channel 2

Supply Voltage

30, 31

PGND 1

Power Ground Channel 1

ST 1

Status Output Channel 1

IN 3

Control Input Channel 3

IN 1

Control Input Channel 1

ST 3

Status Output Channel 3

CLK

Clock Input

L9347

4/21

ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is sub-
jected to conditions which are beyond these values.

THERMAL DATA

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Switch off energy for inductive loads

Voltages

Supply voltage

-0.3

, V

Supply voltage

-0.3

Output voltage static

Output voltage during clamping

t < 1ms

, V

Input voltage IN1 to IN4, EN

< |10|mA

-1.5

CLK

Input Voltage CLK

-1.5

Output voltage status

-0.3

Recirculation circuits D3, D4

DRmax

max. reverse breakdown voltage of free
wheeling diodes D3, D4

Currents

Q1/2

Output current for Q1 and Q2

internal

limited

Q3/4

Output current for Q3 and Q4

internal

limited

Q1/2

PGND1/2

Output current at reversal supply for Q1
and Q2

-4

Q3/4

PGND3/4

Output current at reversal supply for
Q3 and Q4

-2

Output current status pin

-5

ESD Protection

ESD

Electrostatical Discharging

MIL883C

�

ESD

Output Pins (Qx, Dx)

vs. Common GND
(PGND1-4 + GND)

�

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Junction temperature

-40

150

�C

Junction temperature during clamping
(life time)

t = 30min

t = 15min

175
190

�C

stg

Storage temperature

stg

-55

150

�C

Overtemperature shutdown threshold

(1)

(1) This parameter will not be tested but assured by design.

175

200

�C

Overtemperature shutdown hysteresis

(1)

�C

thJC

Thermal resistance junction to case

thJC

K/W

5/21

L9347

OPERATING RANGE

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply voltage

4.8

, V

Supply voltage

4.5

5.5

/dt

Supply voltage transient time

-1

�

Output voltage static

-0.3

Output voltage induced by inductive switching

Voltage will be
limited by internal
Z-diode clamping

Output voltage status

-0.3

Output current status

-1

Junction temperature

-40

150

�C

Junction temperature during clamping

= 30min

= 15min

175
190

�C

ELECTRICAL CHARACTERISTCS:
(Vs = 4.8 to 18V; T

= -40 to 150�C unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Power Supply

SON

Supply current

18V

(outputs ON)

SOFF

Quiescent current

18V

(outputs OFF)

Supply current VCC (analog supply)

VCC =5V

Supply current VDD (digital supply)

VDD =5V f

CLK

=0Hz

Supply current VDD (digital supply)

VDD =5V f

CLK

=250kHz

General Diagnostic Functions

Open load voltage

6.5V

(outputs OFF)

0.3

0.33

0.36

x V

thGND

Signal-GND-loss threshold

VCC= 5V

0.1

thPGL

Power-GND-loss threshold

VCC= 5V

1.5

2.5

3.5

CLK,min

Clock frequency error

100

kHz

CLKe_l

Clock duty cycle error detection low

CLK

= 250 kHz

33,3

CLKe_

high

Clock duty cycle error detection high

CLK

= 250 kHz

66,6

loss

Supply detection

VCC = VDD = 5V

4.5

Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels)

QU1,2

Open-load current channel 1, 2

6.5V

140

QO1,2

Over-load current channel 1, 2

6.5V

7.5

L9347

6/21

Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)

OUT

Output duty cycle range

filtered with 10ms

QO3,4

Overload current
channel 3,4

6.5V

2.5

rerr

Recirculation error shutdown
threshold (open D3/D4)

Iout > 50mA

PWM

dOU

Output PWM ratio during drift
comparison

IN3

= V

IN4

= PWM

TEST

= H

-14.3

+14.3

Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%

Input low voltage

-0.3

Input high voltage

IHy

Input voltage hysteresis

(1)

500

Input pull down current

= 5V, V

6.5V

�

Digital Outputs (ST1 to ST4)

STL

Status output voltage in low state

(2)

�

0.4

STH

Status output voltage in high state

-40

�

2.5

3.45

-120

�

3.45

DIAGL

OUT

+ R

DSON

in low state

0.3

0.64

1.5

DIAGH

OUT

+ R

DSON

in high state

1.5

3.2

7.0

Power Outputs (Q1 to Q4)

DSON1,2

Static drain-source ON-resistance
Q1 and Q2
(non-reg. channels)

= 1A; V

9.5V

= 25�C

= 125�C

(3)

= 150�C

(4)

0.2

0.5
0.5

DSON3,4

Static drain-source ON-resistance
Q3 and Q4
(reg. channels)

= 1A; V

9.5V

= 25�C

= 125�C

= 150�C

0.35

0.75
0.75

F_250mA

Forward voltage of free wheeling path
D3, D4 @250mA

D3/4

= -250mA

0.5

1.5

F_2.25A

Forward voltage of free wheeling path
D3, D4 @2.25A

D3/4

= -2.25A

2.0

4.5

sens

Sense resistor = (V

F_2.25A-

F_250mA

ELECTRICAL CHARACTERISTCS: (continued)
(Vs = 4.8 to 18V; T

= -40 to 150�C unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

7/21

L9347

Z-diode clamping voltage

100mA

Output pull down current

= H, V

= L

150

�

Qlk

Output leakage current

= L; V

= 20V

�

Timing

Output ON delay time

= 1A

�

OFF

Output OFF delay time channel

= 1A

�

OFFREG

Output OFF delay time regulator

(5)

528

�

Output rise time

= 1A

0.5

1.5

�

Output fall time

= 1A

0.5

1.5

�

Short error detection filter time

CLK

= 250kHz DC = 50%

(5)

�

Long error detection filter time

CLK

= 250kHz DC = 50%

(5)

�

SCP

Short circuit switch-OFF delay time

(5)

�

Status delay time

(5)

896

1024

Regulation error status delay time

(5)

(reg. channels only)

Dreg

Output off status delay time

(5)

(reg. channels only

528

�

Reg. Current Accuracy (reg. channels only)

Q3/Q4

Minimum current

DC = 10%

200

250

300

Q3/Q4

Maximum current

DC = 90%

2.25

2.5

REG

Max. regulation deviation @
DC 10% - 90%

250mA < I

Q3/Q4

< 400mA

400mA

Q3/Q4

800mA

800mA < I

Q3/Q4

< 2.25A

�10

�6

�10

%
%
%

Q3/Q4

Min. quant. step

Frequencies

CLK frequency

crystal-controlled

250

kHz

Input PWM frequency

(reg. channels only)

kHz

(1) This parameter will not be tested but assured by design
(2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
(3) Measured chip, bond wires not included
(4) Measured on Power SO-36 devices
(5) Digital filtered with external clock, only functional test

ELECTRICAL CHARACTERISTCS: (continued)
(Vs = 4.8 to 18V; T

= -40 to 150�C unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

L9347

8/21

1.0

Functional Description

1.1

Overview

The L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Inte-
grated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recircu-
lation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and
supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and over-
temperature. For each channel one independent push-pull status output is used for a parallel diagnostic func-
tion.

Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The
output current is controlled through the output PWM of the power stage. The regulator limits of 10% or 90% are
detected and monitored with the status signal. The current is measured during recirculation phase of the load.

A test mode compares the differences between the two regulators. This "drift" test compares the output PWM
of the regulators. By this feature a drift of the load during lifetime can be detected.

1.2

Input Circuits

The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs
are connected to pull-down current sources.

1.3

Output Stages (not regulated) Channel 1 and 2

The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are
protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to
recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are
internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With
EN=low this current source is switched off, but the open load comparator is still active.

1.4 Current-Regulator-Stages Channel 3 and 4

The current-regulator channels are designed to drive inductive loads. The target value of the current is given by
the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input
PWM and the output current and the specified accuracy.

Figure 3. Input PWM to output current range

250

2250

r
r
e

t
[

]

INPUT PWM[%]

400

t pr

800

�10%

+- 6%

+-10%

9/21

L9347

The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock.
For requested precision of the output current the ratio between the frequencies of the input signal and the ex-
ternal 250kHz clock has to be fixed according to the graph shown in Fig.

Figure 4. Current accuracy according to the input and clock frequency ratio

The theoretical error is zero for f

CLK

/ f

= 125.

If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For
a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision appli-
cations the clock frequency and the input frequency have to be correlated.

The output current is measured during the recirculation of the load. The current sense resistor is in series to the
free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output
remains low for the rest of the input cycle.

The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is
3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output
and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of
the power is 256

�

s after the first negative edge of the input signal.

As regulator a digital PI-regulator with the Transfer function for:

KI:

and KP: 0.96

for a sampling time of 256us is realised.

To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current
value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90%
during the regulation. The status output gets low if the target current value is not reached within the regulation
error delay time of

=10ms. The output PWM is than out of the regulation range from 10% to 90%.

1.5

Protective Circuits

The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock
is monitored by a clock watchdog. This clock watchdog detects a minimal frequency

CLK,min

and wrong clock

duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected

-10%

5.6%

112.5

132

125

CLK

/ f

t
a

c
cu

c
y

Regulator

switched off

0.126

�

---------------

L9347

10/21

against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage
and invert the status output information.

1.6

Error Detection

The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All ex-
ternal errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).

EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period longer than T

Dreg

and for the standard channel input period longer thanT

A detected error is stored in an error register. The reset of this register is made with a timer T

. With this ap-

proach all errors are present at the status output at least for the time T

All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal "fail" register. The output is then shut off. The register must be reset with a
low signal at the input. A "low signal" means that the input is low for a time longer than T

or T

DReg

for the re-

ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.

Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type
of error is only delayed with the standard timer

function.

Open load is detected for all four channels in on- and off-state.

Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with T

. A sink current stage pull the output down to ground, with EN high. With EN low

the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value I

an open load is

detected and the error register is set and delayed with T

. A regulated channel detects the open load in the on

state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t

than

an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply
voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time
t

, so the output PWM falls below 10%.

A clock failure (clock loss) is detected when the frequency becomes lower than

CLK,min

. All status outputs are

ON State

EN &IN = HIGH

OFF State

EN &IN = LOW

Filter time

Reset done by

Short circuit of the load

EN & IN = "LOW"

for

Dreg

Open load
(under voltage detection)

timer

Open load
(under current detection)

timer

Overtemperature

EN & IN = "LOW"

for

Dreg

Power-GND-loss

in on: EN & IN = "LOW"

for

Dreg

in off: timer

Signal-GND-loss

timer

Supply-VS-loss

timer

Clock control

in on: EN & IN = "LOW"

for

Dreg

in off: timer

Output voltage clamp active

(regulated

channels)

in on: EN & IN = "LOW"

for

Dreg

in off: timer

11/21

L9347

set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.

1.7

Drift Detection (regulated channels only)

The drift detection is used to compare the two regulated channels during regulation. This "Drift" test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated for-
mula for the output current below shows the dependency of the load resistor to the output PWM. In this formula
the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The test-
mode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the
output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than �14.3% of
the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with T

as other errors

A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.

1.8

Other Test modes

The test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indi-
cation of a proper logic functionality. The following table shows the functionality of this special test mode

For more details about the test condition four see timing diagram.

TEST

OUT

STATUS

Note

disable test mode

Drift mode

off

test pattern

test condition one

off

test pattern

test condition two

off

test pattern

test condition three

off

test pattern

test condition four

test pattern

test condition four

IOUT

VBAT

RON

----------------------------

PWM

Drift Definition:

Drift = PWM(1+E) - PWM (1-E) = 2PWM E

Drift * 4 < PWM (1+E)

with E >14.3% a drift is detected

E.. not correlated Error of the channels

%PWM ... Corresponding ideal output PWM to a given input PWM

L9347

12/21

Diagnostic Table

The status follows the input signal in normal operating conditions.

If any error is detected the status is inverted.

Operating Condition

Test

Input

TEST

Enable

Input

ENA

Control Input

non-reg./reg.

Power Output/

Current reg.

Status

Output

Normal function

L
L
L
L

L
L

H
H

H/PWM

OFF
OFF
OFF

L
L
L

Open load or short to ground

L
L
L
L

L
L

H
H

H/PWM

OFF
OFF
OFF

X
X
H

Overload or short to supply

Latched overload
Reset latch
Reset latch

L
L
L
L

H
H

H �> L

H/PWM
H/PWM

H/PWM �> L

OFF
OFF
OFF
OFF

L
L
L
L

Overtemperature

Latched overtemperature
Reset latch
Reset latch

L
L
L
L

H
H

H �> L

H/PWM
H/PWM

H/PWM �> L

OFF
OFF
OFF
OFF

L
L
L
L

Recirculation error (reg.chn.)

Latched error
Reset latch
Reset latch

L
L
L
L

H
H

H �> L

PWM
PWM

PWM �> L

OFF
OFF
OFF
OFF

L
L
L
L

Clock failure (clock loss)

(1)

(1) during power on sequence only detected on channel 3 and 4 (see description).

L
L
L
L

L
L

H
H

H/PWM

OFF
OFF
OFF
OFF

H
H
H

Drift

(2)

Failure
No failure

(2) This input combination is also used for an internal chip-test and must not be used.

H
H
H
H

L
L

H
H

H/PWM
H/PWM
H/PWM

OFF
OFF

ON
ON

X
X

L9347

20/21

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

3.60

0.141

0.10

0.30

0.004

0.012

3.30

0.130

0.10

0.004

0.22

0.38

0.008

0.015

0.23

0.32

0.009

0.012

D (1)

15.80

16.00

0.622

0.630

9.40

9.80

0.370

0.385

13.90

14.50

0.547

0.570

0.65

0.0256

11.05

0.435

E1 (1)

10.90

11.10

0.429

0.437

2.90

0.114

5.80

6.20

0.228

0.244

2.90

3.20

0.114

0.126

0.10

0.004

15.50

15.90

0.610

0.626

1.10

0.043

0.80

1.10

0.031

0.043

�

(max.)

�

(max.)

(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".

PowerSO36

PSO36MEC

DETAIL A

h x 45�

DETAIL A

lead

slug

Gage Plane

0.35

DETAIL B

(COPLANARITY)

- C -

SEATING PLANE

0.12

A B

BOTTOM VIEW

OUTLINE AND

MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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L9347

Электронный компонент: L9347PD