L9610C
L9611C
November 1991
PWM POWER MOS CONTROLLER
.
HIGH EFFICIENCY DUE TO PWM CONTROL
AND POWERMOS DRIVER
.
LOAD DUMP PROTECTION
.
LOAD POWER LIMITATION
.
EXTERNAL POWERMOS PROTECTION
.
LIMITED OUTPUT VOLTAGE SLEW RATE
SO16
DESCRIPTION
The L9610C/11C is a monolithic integrated circuit
working in PWM mode as controller of an external
powerMOS transistor in High Side Driver configura-
tion.
Features of the device include controlled slope of
the leading and trailing edge of the gate driving vol-
tage, linear current limiting with protection timer, set-
table switching frequencyfo, TTL compatible enable
function, protection status ouput pin. The device is
mounted in SO16 micropackage, and DIP16 pack-
age.
ORDERING NUMBERS: L9610C
L9611C
BLOCK DIAGRAM
1/9
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DIP 16
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Max. Supply Voltage
26
V
Transient Peak Supply Voltage (R1
100
):
Load Dump:
5ms
t
rise
10ms;
f
Fall Time Constant = 100ms; R
SOURCE
0.5
Field Decay:
5ms
t
fall
10ms;
r
Rise Time Constant = 33ms; R
SOURCE
10
Low Energy Spike: t
rise
=1
s, t
fall
= 2ms, R
SOURCE
10
60
80
100
V
V
V
I
S
Max. Supply Current (t < 300 ms)
0.3
A
V
IN
Input Voltage
0.3 < V
IN
< V
S
2.5
V
T
J
/T
stg
Junction and Storage Temperature Range
55 to 150
C
THERMAL DATA
Symbol
Parameter
SO16
DIP16
Value
R
th j-amb
Thermal Resistance Junction-alumina
Max
50
90
C/W
L9610C - L9611C
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PIN FUNCTIONS
Pin
Name
Functions
1
INT
A Capacitor Connected Between this Pin and Out
G
Defines the GATE
Voltage Slew Rate.
2
IN
Analog Input Controlling the PWM Ratio. The operating range of the input
voltage is 0 to V
R
.
3
V
R
Output of an Internal Voltage Reference
4
EN
TTL Compatible Input for Switching off the Output.
5
PWL
If this Pin is Connected to GND and V
S
> 13 V, the Duty Cycle and the
Frequency f
o
are Reduced : this Allows to Transfer a Costant Power to the
Load.
6
Osc
Current Sink and Source Stage Connection of a Triangle Oscillator with
Definite Voltage Swing.
7
IND
Input of an Operational Amplifier for Short Current Sensing and Regulation.
8
NC
Not Connected.
9
V
S
Common Supply Voltage Input
10
GND
Common Ground Connection
11
TIM
A Capacitor Connected Between this Pin and GND Defines the Protection
Delay Time.
12
MON
Open Collector Monitoring Output off the PowerMOS Protection.
13,15
P2, P1
Connection for the Charge Pump Capacitor.
14
BS
The Capacitor Connected Between thisPin and theSource of the Power MOS
Allows to Bootstrap the Gate Driving Voltage.
16
Out G
Output for Driving the Gate of the External PowerMOS.
L9610C - L9611C
3/12
ELECTRICAL CHARACTERISITCS (T
amb
= 40
C to 85
C ; 6 V < V
S
< 16 V unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
S
Operating Supply Voltage
6
16
V
I
q
Quiescent Current
2.5
6
mA
V
SC
Internal Supply Voltage Clamp
I
S
= 200mA
28
32
36
V
V
SH
Supply Voltage High Threshold
16
18.5
21
V
V
SL
Supply Voltage Low Threshold
4
5
6
V
V
R
Reference Voltage
3.3
3.5
3.7
V
I
R
Reference Current
V
R
100mV
1
mA
V
INL
Input Low Threshold
0.13
0.15
0.2
V
IN
/V
R
K
F
Oscillator Freq. Constant
Note 1
800
2500
nF/s
K
S
Gate Voltage Slew Rate
Constant
Note 2
3
5
9
nFV/ms
K
T
Protection Time Delay Constant
Note 3
0.12
0.44
ms/nF
V
Si
Sense Input Volt.
80
100
120
mV
V
GON
Gate Driving Volt. above V
S
V
S
= 16V
8
16
V
V
GOFF
Gate Voltage in OFF Condition
I
G
= 100
A
1.2
V
I
IN
Input Current
5
1
A
V
ENL
Low Enable Voltage
0.8
V
V
ENH
High Enable Voltage
2.0
V
IEN
Enable Input Current
2
A
SR
Slew Rate
Without C
S
0.5
V/
s
V
MONsat
Saturation Voltage (pin 12)
I
MON = 2.5 mA
1.5
V
Notes :
1. f
o
= K
F
/C
F
.
2. dV
G
/dt = Ks/Cs.
3. t
prot
= K
T
C
T
.
FUNCTIONAL DESCRIPTION
PULSE WIDTH COMPARATOR
A ground compatible comparator generates the
PWM signal which controls the gate of the external
powerMOS.
The slopes of the leading and trailing edges of the
gate driving signal are defined by the external ca-
pacitor C
S
according to :
dV
G
/dt = K
S
/C
S
This feature allows to optimize the switching speed
for the power and RFI performance best suited for
the application.
The lower limit of the duty cycle is fixed at 15 % of
the ratio between the input and the reference vol-
tage (see fig. 1). Input voltages lower than this value
disable the internal oscillator signal and therefore
the gate driver.
GROUND COMPATIBLE TRIANGLE
OSCILLATOR
The triangle oscillator provides the switching fre-
quency f
o
set by the external capacitor C
F
according
to :
f
o
= K
F
/C
F
If the pin PWL (power limitation) is connected to
ground and Vs is higher than the PWL threshold
voltage, the duty cycle and the f
o
frequency are re-
duced : this allows to transfer a costant power to the
load (see fig. 2).
TIMER AND PROTECTION LATCH
When an overcurrent occurs, the device starts
charging the external capacitor C
T
; the protection
time is set according to :
t
prot
= K
T
.
C
T
L9610C - L9611C
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After the overcurrent protection time is reached, the
powerMOS is switched-off ; this condition is latched
by setting an internal flip-flop and is externallymoni-
tored by the low state of the MON pin.
To resetthe latch the supply voltage hasto fall below
V
SL
or the device must be switched off.
UNDER AND OVERVOLTAGE SENSE WITH
LOAD DUMP PROTECTION
The undervoltage detection feature resets the timer
and switches off the output driving signal when the
supply voltage is less than V
SL
.
If the supply voltage exceeds the max operating
supply voltage value, an internal comparator dis-
ables the charge pump, the oscillator and the exter-
nal powerMOS.
In both cases the thresholds are provided with suit-
able hysteresis values.
The load dump protection function allows the device
to withstand - for a limited time - high overvoltages.
It consists of an active clamping diode which limits
the circuit supply voltage to V
CLAMP
and an external
current limiting resistor R1. The maximum pulse
supply current (see abs. max. ratings is equal to
0.3A. Therefore the maximum load dump voltage is
given by :
V
DUMP
= V
SC
+ 0.3R
1
In this condition the gate of the powerMOS is held
at the GND pin potential and thus the load voltage
is :
V
L
= Vs - V
CLAMP
- V
GS
Figure 1 : Typical Transfer Curve.
L9610C - L9611C
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