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Электронный компонент: L9950

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1/23
L9950
July 2004
1
FEATURES
One full bridge for 6A load (r
on
= 150m
)
Two half bridges for 3A load (r
on
= 300m
)
Two half bridges for 1.5A load (r
on
= 800m
)
One highside driver for 6A load (r
on
= 100m
)
Four highside drivers for 1.5A load (r
on
= 800 m
)
Programmable Softstart function to drive loads
with higher inrush currents (i.e. current
>6A,>3A,>1.5A)
Very low current consumption in standby mode
I
S
< 6
A, typ. Tj
85 C)
All outputs short circuit protected
Current monitor output for 300m
,150m
and
100m highside drivers
All outputs over temperature protected
Open load diagnostic for all outputs
Overload diagnostic for all outputs
Seperated half bridges for door lock motor
PWM control of all outputs
Charge Pump output for reverse polarity
protection
2
APPLICATIONS
Door Actuator Driver with bridges for door lock and
safe lock, mirror axis control, mirror fold and highside
driver for mirror defroster and four 5W-light bulbs.
3
DESCRIPTION
The L9950 is a microcontroller driven multifunc-
tional door actuator driver for automotive applica-
tions.Up to five DC motors and five grounded
resistive loads can be driven with six half bridges
and five highside drivers. The integrated standard
serial peripheral interface (SPI) controls all opera-
tion modes (forward, reverse, brake and high im-
pedance).
All diagnostic informations are available via SPI.
DOOR ACTUATOR DRIVER
Figure 2. Block Diagram
DI
CM/PWM2
DO
CLK
CSN

C
C
VCC
VBAT
PWM1
SPI
D
r
i
v
er
Inte
r
f
ac
e &
D
i
agn
os
ti
c
GND
M
M
CP
MU
X
VS
Exteriour Light
Turn Indicator
Safety Light
Footstep Light
Defroster
Lock
Safe Lock
xy-Mirror
Motors
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
M
M
M
M
M
M
100k
Reverse
Polarity
Protection
PWM2
M
M
Mirror Fold
Note: value of capacitor has to be
choosen carefully to limit the VS
voltage below absolute maximum
ratings in case of an unexpected
freewheeling condition (e.g. TSD,
POR)
1k
1k
1k
1k
1k
1k
Note: resistors between

C and
L9950 are recommended to limit
currents for negative voltage
transients at VBAT (e.g. ISO
type 1 pulse).
10k
REV. 3
Figure 1. Package
Table 1. Order Codes
Part Number
Package
L9950
PowerSO36
L9950TR
Tape & Reel
PowerSO36
L9950
2/23
3.1
Dual Power Supply: V
S
and V
CC
The power supply voltage V
S
supplies the half bridges and the highside drivers. An internal charge-pump
is used to drive the highside switches. The logic supply voltage V
CC
(stabilized 5 V) is used for the logic
part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be lost, if there are
temporary spikes or glitches on the power supply voltage. In case of power-on (V
CC
increases from und-
ervoltage to V
POR OFF
= 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If
the voltage V
CC
decreases under the minimum threshold (V
POR ON
= 3.4 V), the outputs are switched to
tristate (high impedance) and the status registers are cleared.
3.2
Standby-Mode
The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data Register 0. All latched
data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the
current at V
S
(V
CC
) is less than 6 A (50A) for CSN = high (DO in tristate). By switching the V
CC
voltage
a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.
3.3
Inductive Loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due
to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1
to OUT6 without external free-wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive
resistive loads. Hence only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in free-
wheeling condition. For inductive loads (L>100
H) an external free-wheeling diode connected to GND and
the corresponding output is needed.
3.4
Diagnostic Functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and ther-
mal shutdown) are internally filtered and the condition has to be valid for at least 32 s (open load: 1ms,
respectively) before the corresponding status bit in the status registers will be set. The filters are used to
improve the noise immunity of the device. Open load and temperature warning function are intended for
information purpose and will not change the state of the output drivers. On contrary, the overload and ther-
mal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bits in the Input Data Register, the microcontroller
has to clear the over-current status bits to reactivate the corresponding drivers.
3.5
Overvoltage and Undervoltage Detection
If the power supply voltage V
S
rises above the overvoltage threshold V
SOV OFF
(typical 21 V), the outputs
OUT1 to OUT11 are switched to high impedance state to protect the load. When the voltage V
S
drops
below the undervoltage threshold V
SUV OFF
(UV-switch-OFF voltage), the output stages are switched to
the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (in-
creased power dissipation). If the supply voltage V
S
recovers to normal operating voltage the outputs stag-
es return to the programmed state (input register 0: bit 20=0).
If the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deacti-
vated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set
bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery volt-
age.
3.6
Temperature Warning and Thermal Shutdown
If junction temperature rises above T
j TW
a temperature warning flag is set and is detectable via the SPI.
If junction temperature increases above the second threshold T
j SD
, the thermal shutdown bit will be set
and power DMOS transistors of all output stages are switched off to protect the device. In order to reacti-
vate the output stages the junction temperature must decrease below T
j SD
- T
j SD HYS
and the thermal
shutdown bit has to be cleared by the microcontroller.
3/23
L9950
3.7
Open Load Detection
The open load detection monitors the load current in each activated output stage. If the load current is
below the open load detection threshold for at least 1 ms (t
dOL
) the corresponding open load bit is set in
the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the
loads.
3.8
Over Load Detection
In case of an over-current condition a flag is set in the status register in the same way as open load de-
tection. If the over-current signal is valid for at least t
ISC
= 32 s, the over-current flag is set and the cor-
responding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the
over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate
the corresponding driver.
3.9
Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio
(1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data
Register 0 control which of the outputs OUT1, OUT4, OUT5, OUT6 and OUT11 will be multiplexed to the
current monitor output. The current monitor output allows a more precise analysis of the actual state of the
load rather than the detection of an open- or overload condition. For example this can be used to detect
the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the de-
froster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM
inputs).
3.10 PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the
PWM enable bit is set, the output is controlled by the logically AND-combination of the PWM signal and
the output control bit in Input Data Register. The outputs OUT1-OUT8 and OUT11 are controlled by the
PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example,
the two PWM inputs can be used to dim two lamps independently by external PWM signals.
3.11 Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or
HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by
the cross-current protection time. After the cross-current protection time is expired the slew-rate limited
switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on
with slew-rate limitation. Due to this behaviour it is always guaranteed that the previously activated driver
is totally turned-off before the opposite driver will start to conduct.
3.12 Programmable Softstart Function to drive loads with higher inrush currrent
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current
of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e.
overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set,
the device will automatically switch-on the outputs again after a programmable recovery time. The duty
cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The
PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb)
until the load reaches operating condition.
The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real
overload condition can only be qualified by time. As an example the microcontroller can switch on light
bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output
will be automatically disabled if the overload condition still exits
L9950
4/23
Example of programmable softstart function for inductive loads
Figure 3.
Figure 4. Pin Connection
GND 1
OUT11 2
OUT1 3
OUT2 4
OUT3 5
VS 6
VS 7
8
CM/PWM2 9
CSN 10
DO 11
VCC 12
CLK 13
VS 14
VS 15
OUT4 16
OUT4 17
GND 18
DI
GND
36
OUT11
35
OUT10
34
OUT9
33
VS
32
VS
31 OUT8
30
29
VS
28
PWM1
27
CP
26
VS
25
VS
24
VS
23
OUT6
22
OUT5
21
OUT5
20
GND
19
OUT7
Power SO36
Chip
Leadframe
5/23
L9950
Table 2. Pin Description
Pin
Symbol
Function
1, 18, 19,
36
GND
Ground:
Reference potential
Important: For the capability of driving the full current at the outputs all pins of GND must
be externally connected !
2.35
OUT11
Highside-driver-output 11:
The output is built by a highside switch and is intended for resistive loads, hence the
internal reverse diode from GND to the output is missing. For ESD reason a diode to GND
is present but the energy which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-
diode). The output is over-current and open load protected.
Important: For the capability of driving the full current at the outputs both pins of OUT11
must be externally connected !
3
4
5
OUT1
OUT2
OUT3
Halfbridge-output 1,2,3:
The output is built by a highside and a lowside switch, which are internally connected. The
output stage of both switches is a power DMOS transistor. Each driver has an internal
parasitic reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver
from GND to output). This output is over-current and open load protected.
6, 7, 14, 15,
23, 24, 25,
28, 29, 32
VS
Power supply voltage (external reverse protection required):
For this input a ceramic capacitor as close as possible to GND is recommended.
Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected !
8
DI
Serial data input:
The input requires CMOS logic levels and receives serial data from the microcontroller.
The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred
first.
9
CM/PWM2
Current monitor output/PWM2 input:
Depending on the selected multiplexer bits of Input Data Register this output sources an
image of the instant current through the corresponding highside driver with a ratio of 1/
10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the outputs OUT9 and OUT10.
10
CSN
Chip Select Not input / Testmode :
This input is low active and requires CMOS logic levels. The serial data transfer between
L9950 and micro controller is enabled by pulling the input CSN to low level. If an input
voltage of more than 7.5V is applied to CSN pin the L9950 will be switched into a test
mode.
11
DO
Serial data output:
The diagnosis data is available via the SPI and this tristate-output. The output will remain
in tristate, if the chip is not selected by the input CSN (CSN = high)
12
VCC
Logic supply voltage:
For this input a ceramic capacitor as close as possible to GND is recommended.
13
CLK
Serial clock input:
This input controls the internal shift register of the SPI and requires CMOS logic levels.
16,17,
20,21,
22
OUT4
OUT5
OUT6
Halfbridge-output 4,5,6:
see OUT1 (pin 3).
Important: For the capability of driving the full current at the outputs both pins of OUT4
(OUT5, respectively) must be externally connected !
26
CP
Charge Pump Output:
This output is provided to drive the gate of an external n-channel power MOS used for
reverse polarity protection (see FIGURE 1)
27
PWM1
PWM1 input:
This input signal can be used to control the drivers OUT1-OUT8 and OUT11 by an
external PWM signal.
30
31
33
34
OUT7,
OUT8,
OUT9,
OUT10
Highside-driver-output 7,8,9,10:
The output is built by a highside switch and is intended for resistive loads, hence the
internal reverse diode from GND to the output is missing. For ESD reason a diode to GND
is present but the energy which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-
diode). The output is over-current and open load protected.
L9950
6/23
Table 3. Absolute Maximum Ratings
Note
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the
integrated circuit !
Table 4. Esd Protection
Note: 1. HBM according to CDF-AEC-Q100-002
2. HBM with all unzapped pins grounded
Table 5. Thermal Data
Table 6. Temperature warning and thermal shutdown
Symbol
Parameter
Value
Unit
V
S
DC supply voltage
-0.3 to28
V
single pulse t
max
< 400ms
40
V
V
CC
stabilized supply voltage, logic supply
-0.3 to 5.5
V
V
DI
V
DO
V
CLK
V
CSN,
V
pwm1
digital input / output voltage
-0.3 to V
CC
+ 0.3
V
V
CM
current monitor output
-0.3 to V
CC
+ 0.3
V
V
CP
charge pump output
-25 to V
S
+ 11
V
I
OUT1,2,3,6,7,8,9,10
output current
5
A
I
OUT4,5,11
output current
10
A
Parameter
Value
Unit
All pins
4
1
kV
output pins: OUT1 - OUT11
8
2
kV
Symbol
Parameter
Value
Unit
T
j
Operating junction temperature
-40 to 150
C
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
jTW ON
temperature warning threshold junction temperature
T
j
increasing
150
C
T
jTW OFF
temperature warning threshold junction temperature
T
j
decreasing
130
C
T
jTW HYS
temperature warning hysteresis
5
K
T
jSD ON
thermal shutdown threshold junction temperature
T
j
increasing
170
C
T
jSD OFF
thermal shutdown threshold junction temperature
T
j
decreasing
150
C
T
jSD HYS
thermal shutdown hysteresis
5
K
7/23
L9950
Figure 5. Thermal Data Of Package
Table 7. ELECTRICAL CHARACTERISTICS
(V
S
= 8 to 16V, V
CC
= 4.5 to 5.3V, T
j
= - 40 to 150 C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply
V
S
operating supply voltage range
7
28
V
I
S
VS DC supply current
V
S
= 16V, V
CC
= 5.3V
active mode
OUT1 - OUT11 floating
7
20
mA
VS quiescent supply current
V
S
= 16V, V
CC
= 0V
standby mode
OUT1 - OUT11 floating
T
test
=-40C, 25C
4
12
A
I
CC
VCC DC supply current
V
S
= 16V, V
CC
= 5.3V
CSN = V
CC
active mode
1
3
mA
VCC quiescent supply current
V
S
= 16V, V
CC
= 5.3V
CSN = V
CC
standby mode
OUT1 - OUT11 floating
25
50
A
I
S
+ I
CC
sum quiescent supply current
V
S
= 16V, V
CC
= 5.3V
CSN = V
CC
standby mode
OUT1 - OUT11 floating
31
75
A
Over- and undervoltage detection:
V
SUV ON
VS UV-threshold voltage
V
S
increasing
5.9
7.2
V
V
SUV OFF
VS UV-threshold voltage
V
S
decreasing
5.5
6.5
V
V
SUV hyst
VS UV-hysteresis
V
SUV ON
- V
SUV OFF
0.5
V
V
SOV OFF
VS OV-threshold voltage
V
S
increasing
18
24.5
V
L9950
8/23
V
SOV ON
VS OV-threshold voltage
V
S
decreasing
17.5
22
V
V
SOV hyst
VS OV-hysteresis
V
SOV OFF
- V
SOV ON
1
V
V
POR OFF
power-on-reset threshold
V
CC
increasing
4.4
V
V
POR ON
power-on-reset threshold
V
CC
decreasing
3.1
V
V
POR hyst
power-on-reset hysteresis
V
POR OFF
- V
POR ON
0.3
V
Current Monitor Output
V
CM
functional voltage range
V
CC
= 5V
0
4
V
I
CM,r
current monitor output ratio:
I
CM
/ I
OUT1,4,5,6,11
0V
V
CM
4V, VCC=5V
-
I
CM acc
current monitor accuracy
0 V
V
CM
3.8V,
V
CC
= 5V, I
Out,min
=500mA,
I
Out4,5,11,max
= 5.9A
I
Out1,6,max
=2.9A
(FS = full scale=600
A)
4% +
1%FS
8% +
2%FS
-
Change Pump Output:
V
CP
charge pump output voltage
V
S
=8V, I
CP
=-60
A
6
13
V
V
S
=10V, I
CP
=-80
A
8
13
V
V
S
12V, I
CP
=-100
A
10
13
V
I
CP
charge pump output current
V
CP
= V
S
+10V, V
S
=13.5V
95
150
300
A
Outputs: OUT1 - OUT2
r
ON OUT1,
r
ON
OUT6
on-resistance to supply or GND
V
S
= 13.5 V, T
j
= 25 C,
I
OUT1,6
=
1.5A
300
400
m
V
S
= 13.5 V, T
j
= 125 C,
I
OUT1,6
=
1.5 A
450
600
m
V
S
= 8.0 V, T
j
= 25 C,
I
OUT1,6
=
1.5 A
300
400
m
r
ON OUT2,
r
ON OUT3
on-resistance to supply or GND
V
S
= 13.5 V, T
j
= 25 C,
I
OUT2,3
=
0.8A
800
1100
m
V
S
= 13.5 V, T
j
= 125 C,
I
OUT2,3
=
0.8 A
1250
1700
m
V
S
= 8.0 V, T
j
= 25 C,
I
OUT2,3
=
0.8 A
800
1100
m
r
ON OUT4,
r
ON
OUT5
on-resistance to supply or GND
VS = 13.5 V, T
j
= 25 C,
I
OUT4,5
=
3.0 A
150
200
m
V
S
= 13.5 V, T
j
= 125 C,
I
OUT4,5
=
3.0 A
225
300
m
V
S
= 8.0 V, T
j
= 25 C,
I
OUT4,5
=
3.0 A
150
200
m
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(V
S
= 8 to 16V, V
CC
= 4.5 to 5.3V, T
j
= - 40 to 150 C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1
10.000
------------------
9/23
L9950
r
ON OUT7,
r
ON
OUT8,
r
ON OUT9
,
r
ON OUT10
on-resistance to supply
V
S
= 13.5 V, T
j
= 25 C,
I
OUT7,8,9,10
= -0.8 A
800
1100
m
V
S
= 13.5 V, T
j
= 125 C,
I
OUT7,8,9,10
= -0.8 A
1250
1700
m
V
S
= 8.0 V, T
j
= 25 C,
I
OUT7,8,9,10
= -0.8 A
800
1100
m
r
ON OUT11
on-resistance to supply
V
S
= 13.5 V, T
j
= 25 C,
I
OUT11
= - 3.0 A
100
150
m
V
S
= 13.5 V, T
j
= 125 C,
I
OUT11
= - 3.0A
150
200
m
V
S
= 8.0 V, T
j
= 25 C,
I
OUT11
= - 3.0 A
100
150
m
|I
OUT1
|, |I
OUT6
| output current limitation to supply
or GND
sink and source, V
S
=13.5V
3
5
A
|I
OUT2
|, |I
OUT3
| output current limitation to supply
or GND
sink and source, V
S
= 13.5V
1.5
2.5
A
|I
OUT4
|, |I
OUT5
| output current limitation to supply
or GND
sink and source, V
S
= 13.5V
6
10
A
|I
OUT7
|, |I
OUT8
|,
|I
OUT9
|,
|I
OUT10
|
output current limitation to GND
source, V
S
= 13.5V
1.5
2.5
A
|I
OUT11
|
output current limitation to GND
source, V
S
= 13.5V
6
10
A
t
d ON H
output delay time,
highside driver on
V
S
= 13.5 V, corresponding
lowside driver is not active
20
40
80
s
t
d OFF H
output delay time,
highside driver off
V
S
= 13.5 V
50
150
300
s
t
d ON L
output delay time,
lowside driver on
V
S
= 13.5 V, corresponding
highside driver is not active
15
30
70
s
t
d OFF L
output delay time,
lowside driver off
V
S
= 13.5 V
80
150
300
s
t
D HL
cross current protection time,
source to sink
t
d ON L
- t
d OFF H,
200
400
s
t
D LH
cross current protection time,
sink to source
t
d ON H
- t
d OFF L
200
400
s
I
QLH
switched-off output current
highside drivers of OUT1-11
V
OUT1-11
=0V, standby mode
0
-2
-5
A
V
OUT1-11
=0V, active mode
-40
-15
0
A
I
QLL
switched-off output current
lowside drivers of OUT1-6
V
OUT1-6
= V
S
, standby mode
0
80
120
A
V
OUT1-6
=V
S
, active mode
-40
-15
0
A
I
OLD1
open load detection current of
OUT1
5
30
80
mA
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(V
S
= 8 to 16V, V
CC
= 4.5 to 5.3V, T
j
= - 40 to 150 C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
L9950
10/23
4
FUNCTIONAL DESCRIPTION OF THE SPI
4.1
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a mi-
crocontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is
changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins
and one input pin will be needed to communicate with the device. A fault condition can be detected by
setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which
is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device
without the need of a full SPI-communication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see FIGURE 6).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO)
will be in high impedance state. A low signal will activate the output driver and a serial communication can
be started. The state when CSN is going low until the rising edge of CSN will be called a communication
frame. If the CSN-input pin is driven above 7.5V, the L9950 will go into a test mode. In the test mode the
DO will go from tri-state to active mode.
I
OLD23
open load detection current of
OUT2, OUT3
15
40
60
mA
I
OLD45
open load detection current of
OUT4 and OUT5
60
150
300
mA
I
OLD6
open load detection current of
OUT6
30
70
150
mA
I
OLD78910
open load detection current of
OUT7, OUT8, OUT9, OUT10
15
40
60
mA
I
OLD11
open load detection current of
OUT11
30
150
300
mA
t
dOL
minimum duration of open load
condition to set the status bit
500
3000
s
t
ISC
minimum duration of over-current
condition to switch off the driver
10
100
s
dV
OUT16
/dt
slew rate of OUT1,OUT6
V
S
=13.5 V
I
load
= 1.5 A
0.1
0.2
0.4
V/
s
dV
OUT23
/dt,
dV
OUT78910
/dt
slew rate of OUT2/3 and OUT7-
OUT10
V
S
= 13.5 V
I
load
= -0.8 A
0.09
0.2
0.4
V/
s
dV
OUT45
/dt
slew rate of OUT4, OUT5
V
S
= 13.5 V
I
load
= 3.0 A
0.1
0.2
0.4
V/
s
dV
OUT11
/dt
slew rate of OUT11
V
S
= 13.5 V
I
load
= 3.0 A
0.1
0.2
0.4
V/
s
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(V
S
= 8 to 16V, V
CC
= 4.5 to 5.3V, T
j
= - 40 to 150 C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
11/23
L9950
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at
the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the
CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the
selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication
frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be
ignored. This safety function is implemented to avoid an activation of the output stages by a wrong com-
munication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling
the CSN signal of the connected ICs is recommended.
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance
to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input
after a high to low transition of the CSN pin will transfer the content of the selected status register into the
data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sam-
pled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK
signal.
4.6
Input Data Register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input
Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of
the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data
bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO
during the current communication frame. Bit 1-17 controls the behaviour of the corresponding driver.
If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current
monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status
registers will be cleared after the current communication frame (rising edge of CSN).
4.7
Status Register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a
fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be
polled by the microcontroller without the need of a full SPI-communication cycle (see FIGURE 11). If one
of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of
the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal
shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear
the bit to enable the drivers.
4.8
Test Mode
The Test Mode can be entered by rising the CSN input to a voltage higher than 7.0V. In the test mode the
inputs CLK, DI, PWM1/2 and the internal 2MHz CLK can be multiplexed to data output DO for testing pur-
pose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower
current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW
and TSD thresholds.
The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched-
on at the same time. In the testmode this combination is used to multiplex the desired signals according
to following table 8:
L9950
12/23
Table 8.
LS1
HS1
LS2
HS2
LS3
HS3
DO
LS3
HS3
LS4
HS4
LS5
HS5
Test Pad
! (both HI)
! (both HI)
! (both HI)
NoError
! (both HI)
! (both HI)
! (both HI)
5
A Iref
both HI
! (both HI)
! (both HI)
DI
both HI
! (both HI)
! (both HI)
Tsens1
! (both HI)
both HI
! (both HI)
CLK
! (both HI)
both HI
! (both HI)
Tsens2
both HI
both HI
! (both HI)
INT_CLK
both HI
both HI
! (both HI)
Tsens3
! (both HI)
! (both HI)
both HI
PWM1
! (both HI)
! (both HI)
both HI
Tsens4
both HI
! (both HI)
both HI
PWM2
both HI
! (both HI)
both HI
Tsens5
! (both HI)
both HI
both HI
Tsens6
both HI
both HI
both HI
Vbandgap
Table 9. SPI - Input Data and Status Register
Bit
Input Register 0 (write)
Status Register 0 (read)
Name
Comment
Name
Comment
23
Enable Bit
If Enable Bit is set the device
will be switched in active
mode. If Enable Bit is cleared
device go into standby mode
and all bits are cleared. After
power-on reset device starts in
standby mode.
Always 1
A broken VCC-or SPI-connection of
the L9950 can be detected by the
microcontroller, because all 24 bits
low or high is not a valid frame.
22
Reset Bit
If Reset Bit is set both status
registers will be cleared after
rising edge of CSN input.
V
S
overvoltage
In case of an overvoltage or
undervoltage event the
corresponding bit is set and the
outputs are deactivated. If VS
voltage recovers to normal
operating conditions outputs are
reactivated automatically (if Bit 20 of
status register 0 is not set).
21
OC Recovery Duty
Cycle
This bit defines in combination
with the over-current recovery
bit (Input Register 1) the duty
cycle in over-current condition
of an activated driver.
V
S
undervoltage
0: 12%
1: 25%
20
Overvoltage/
Under-voltage
recovery disable
If this bit is set the
microcontroller has to clear the
status register after
undervoltage/overvoltage
event to enable the outputs.
Thermal shutdown
In case of an thermal shutdown all
outputs are switched off.
The microcontroller has to clear the
TSD bit by setting the Reset Bit to
reactivate the outputs.
19
Depending on combination of
bit 18 and 19 the current
image (1/10.000) of the
selected HS-output will be
multi-plexed to the CM output:
Temperature
warning
This bit is for information purpose
only. It can be used for a thermal
management by the microcontroller
to avoid a thermal shutdown.
18
Current Monitor
Select Bits
Bit 19
Bit 18
Output
Not Ready Bit
After switching the device from
standby mode to active mode an
internal timer is started to allow
chargepump to settle before the
outputs can be activated. This bit is
cleared automatically after start up
time has finished. Since this bit is
controlled by internal clock it can be
used for synchonizing testing
events (e.g. measuring filter times).
0
0
OUT11
1
0
OUT1/OUT6
0
1
OUT5
1
1
OUT4
HS-driver of OUT1 is only
selected if HS-driver OUT1 is
switched on and HS-driver
OUT6 is not activated.
13/23
L9950
Table 9. SPI - Input Data and Status Register (continued)
Bit
Input Register 0 (write)
Status Register 0 (read)
Name
Comment
Name
Comment
17
OUT11 HS on/off
If a bit is set the selected
output driver is switched on. If
the corresponding PWM
enable bit is set (Input Register
1) the driver is only activated if
PWM1 (PWM2) input signal is
high. The outputs of OUT1-
OUT6 are half bridges. If the
bits of HS- and LS-driver of the
same half bridge are set, the
internal logic prevents that both
drivers of this output stage can
be switched on simultaneously
in order to avoid a high internal
current from VS to GND. In test
mode (CSN>7.5V) this bit
combinations are used to
multiplex internal signals to the
DO-output.
OUT11 HS over-
current
In case of an over-current event the
corresponding status bit is set and
the output driver is disabled. If the
over-current Recovery Enable bit is
set (Input Register 1) the output will
be automatically reactivated after a
delay time resulting in a PWM
modulated current with a
programmable duty cycle (Bit 21).
If the over-current recovery bit is not
set the microcontroller has to clear
the over-current bit (Reset Bit) to
reactivate the output driver.
16
OUT10 HS on/off
OUT10 HS over-
current
15
OUT9 HS on/off
OUT9 HS over-
current
14
OUT8 HS on/off
OUT8 HS over-
current
13
OUT7 HS on/off
OUT7 HS over-
current
12
OUT6 HS on/off
OUT6 HS over-
current
11
OUT6 LS on/off
OUT6 LS over-
current
10
OUT5 HS on/off
OUT5 HS over-
current
9
OUT5 LS on/off
OUT5 LS over-
current
8
OUT4 HS on/off
OUT4 HS over-
current
7
OUT4 LS on/off
OUT4 LS over-
current
6
OUT3 HS on/off
OUT3 HS over-
current
5
OUT3 LS on/off
OUT3 LS over-
current
4
OUT2 HS on/off
OUT2 HS over-
current
3
OUT2 LS on/off
OUT2 LS over-
current
2
OUT1 HS on/off
OUT1 HS over-
current
1
OUT1 LS on/off
OUT1 LS over-
current
0
0
No error Bit
A logical NOR-combination of all
bits 1 to 22 in both status registers.
Bit
Input Register 1 (write)
Status Register 1 (read)
Name
Comment
Name
Comment
23
Enable Bit
If Enable Bit is set the device will be
switched in active mode. If Enable
Bit is cleared device go into standby
mode and all bits are cleared. After
power-on reset device starts in
standby mode.
Always 1
A broken VCC-or SPI-
connection of the L9950 can
be detected by the
microcontroller, because all
24 bits low or high is not a
valid frame.
Table 9. SPI - Input Data and Status Register (continued)
L9950
14/23
Bit
Input Register 1 (write)
Status Register 1 (read)
Name
Comment
Name
Comment
22
OUT11 OC
Recovery Enable
In case of an over-current event the
over-current status bit (Status
Register 0) is set and the output is
switched off. If the over-current
Recovery Enable bit is set the
output will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable duty
cycle (Bit 21 of Input Data Register
0).
Depending on occurance of
Overcurrent Event and internal
clock phase it is possible that one
recovery cycle is executed even if
this bit is set to zero.
VS overvoltage
In case of an overvoltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.
If VS voltage recovers to
normal operating conditions
outputs are reactivated
automatically.
21
OUT10 OC
Recovery Enable
VS undervoltage
20
OUT9 OC
Recovery Enable
Thermal shutdown
In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear
the TSD bit by setting the
Reset Bit to reactivate the
outputs.
19
OUT8 OC
Recovery Enable
Temperature warning
This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
18
OUT7 OC
Recovery Enable
Not Ready Bit
After switching the device
from standby mode to active
mode an internal timer is
started to allow chargepump
to settle before the outputs
can be activated. This bit is
cleared automatically after
start up time has finished.
Since this bit is controlled by
internal clock it can be used
for synchonizing testing
events(e.g. measuring filter
times).
Table 9. SPI - Input Data and Status Register (continued)
15/23
L9950
Bit
Input Register 1 (write)
Status Register 1 (read)
Name
Comment
Name
Comment
17
OUT6 OC
Recovery Enable
After 50ms the bit can be cleared.
If over-current condition still exists, a
wrong load can be assumed.
OUT11 HS open
load
The open load detection
monitors the load current in
each activated output stage.
If the load current is below
the open load detection
threshold for at least 1 ms
(t
dOL
) the corresponding
open load bit is set. Due to
mechanical/electrical inertia
of typical loads a short
activation of the outputs (e.g.
3ms) can be used to test the
open load status without
changing the mechanical/
electrical state of the loads.
16
OUT5 OC
Recovery Enable
OUT10 HS open
load
15
OUT4 OC
Recovery Enable
OUT9 HS open load
14
OUT3 OC
Recovery Enable
OUT8 HS open load
13
OUT2 OC
Recovery Enable
OUT7 HS open load
12
OUT1 OC
Recovery Enable
OUT6 HS open load
11
OUT11 PWM1
Enable
If the PWM1/2 Enable Bit is set and
the output is enabled (Input Register
0) the output is switched on if
PWM1/2 input is high and switched
off if PWM1/2 input is low. OUT9
and OUT10 is controlled by PWM2
input all other outputs are controlled
by PWM1 input.
OUT6 LS open load
10
OUT10 PWM2
Enable
OUT5 HS open load
9
OUT9 PWM2
Enable
OUT5 LS open load
8
OUT8 PWM1
Enable
OUT4 HS open load
7
OUT7 PWM1
Enable
OUT4 LS open load
6
OUT6 PWM1
Enable
OUT3 HS open load
5
OUT4 PWM1
Enable
OUT3 LS open load
4
OUT4 PWM1
Enable
OUT2 HS open load
3
OUT3 PWM1
Enable
OUT2 LS open load
2
OUT4 PWM1
Enable
OUT1 HS open load
1
OUT4 PWM1
Enable
OUT1 LS open load
0
1
No Error bit
A logical NOR-combination
of all bits 1 to 22 in both
status registers.
Table 9. SPI - Input Data and Status Register (continued)
L9950
16/23
Table 10. SPI - ELECTRICAL CHARACTERISTICS
(V
S
= 8 to 16V, V
CC
= 4.5 to 5.3V, Tj = - 40 to 150 C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin).
Note: 1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
2. DI timing parameters tested in production by a passed/failed test:
Tj=-40C/+25C:
SPI communication @2MHZ
Tj=+125C:
SPI communication @1.25MHZ
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Delay time from standby to active mode
t
set
delay time
Switching from standby to
active mode. Time until
output drivers are enabled
after CSN going to high.
160
300
s
Inputs: CSN, CLK, PWM1/2 and DI
V
inL
input low level
V
CC
= 5V
1.5
2.0
V
V
inH
input high level
V
CC
= 5V
3.0
3.5
V
V
inHyst
input hysteresis
V
CC
= 5V
0.5
V
I
CSN in
pull up current at input CSN
V
CSN
= 3.5V V
CC
= 5V
-40
-20
-8
A
I
CLK in
pull down current at input CLK
V
CLK
= 1.5V
10
25
50
A
I
DI in
pull down current at input DI
V
DI
= 1.5V
10
25
50
A
I
PWM1 in
pull down current at input PWM1
V
PWM
= 1.5V
10
25
50
A
C
in
1
input capacitance at input CSN,
CLK, DI and PWM1/2
V
CC
= 0 to 5.3V
10
15
pF
DI timing (see figure 5 and figure 7)
2
t
CLK
clock period
V
CC
= 5V
1000
ns
t
CLKH
clock high time
V
CC
= 5V
400
ns
t
CLKL
clock low time
V
CC
= 5V
400
ns
t
set CSN
CSN setup time, CSN low before
rising edge of CLK
V
CC
= 5V
400
ns
t
set CLK
CLK setup time, CLK high before
rising edge of CSN
V
CC
= 5V
400
ns
t
set DI
DI setup time
V
CC
= 5V
200
ns
t
hold time
DI hold time
V
CC
= 5V
200
ns
t
r in
rise time of input signal DI, CLK,
CSN
V
CC
= 5V
100
ns
t
f in
fall time of input signal DI, CLK,
CSN
V
CC
= 5V
100
ns
17/23
L9950
Table 10. SPI - ELECTRICAL CHARACTERISTICS
(continued)
3. Value of input capacity is not measured in production test. Parameter guaranteed by design
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DO
V
DOL
output low level
VCC = 5 V, I
D
= -2mA
0.2
0.4
V
V
DOH
output high level
VCC = 5 V, I
D
= 2 mA
V
CC
-0.4
V
CC
-0.2
V
I
DOLK
tristate leakage current
V
CSN
= V
CC
, 0V < V
DO
< V
CC
-10
10
A
C
DO
3
tristate input capacitance
V
CSN
= V
CC
,
0V < V
CC
< 5.3V
10
15
pF
DO timing (see FIGURE 6 and FIGURE 7)
t
r DO
DO rise time
C
L
= 100 pF, I
load
= -1mA
80
140
ns
t
f DO
DO fall time
C
L
= 100 pF, I
load
= 1mA
50
100
ns
t
en DO tri L
DO enable time
from tristate to low level
C
L
= 100 pF, I
load
= 1mA
pull-up load to V
CC
100
250
ns
t
dis DO L tri
DO disable time
from low level to tristate
C
L
= 100 pF, I
load
= 4 mA
pull-up load to V
CC
380
450
ns
t
en DO tri H
DO enable time
from tristate to high level
C
L
=100 pF, I
load
= -1mA
pull-down load to GND
100
250
ns
t
dis DO H tri
DO disable time
from high level to tristate
C
L
= 100 pF, I
load
= -4mA
pull-down load to GND
380
450
ns
t
d DO
DO delay time
V
DO
< 0.3 V
CC
, V
DO
> 0.7 V
CC
,
C
L
= 100pF
50
250
ns
CSN timing (see FIGURE 8)
t
CSN_HI,stb
Minimum CSN HI time, switching
from standby mode
Transfer of SPI-command to
Input Register
20
50
s
t
CSN_HI,min
Maximum CSN HI time, active
mode
Transfer of SPI-command to
Input Register
2
4
s
L9950
18/23
Figure 6. SPI - TRANSFER TIMING DIAGRAM
Figure 7. SPI - INPUT TIMING
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
0
1
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
23
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
19
18
X
X
X
X
X
X
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
0
1
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
1
2
3
4
5
6
7
0
0
1
0
1
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
23
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
19
18
X
X
X
X
X
X
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Valid
Valid
CSN
CLK
DI
t
set CSN
t
CLKH
t
se t CLK
t
CLKL
t
hold DI
t
set DI
19/23
L9950
Figure 8. SPI - DO VALID DATA DELAY TIME AND VALID TIME
Figure 9. SPI - DO ENABLE AND DISABLE TIME
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
CLK
DO
(low to high)
DO
(high to low)
0.5 VCC
t
r in
t
r DO
t
f DO
t
d DO
t
f in
CSN
t
f in
r in
t
DO
DO
en DO tri L
t
t
dis DO L tri
50%
0.8 VCC
0.2 VCC
50%
50%
en DO tri H
t
t
dis DO H tri
C = 100 pF
L
C = 100 pF
L
pull-up load to VCC
pull-down load to GND
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Figure 10. SPI - DRIVER TURN ON/OFF TIMING, MINIMUM CSN HI TIME
Figure 11. SPI - TIMING OF STATUS BIT 0 (FAULT CONDITION)
CSN
dON
t
20%
80%
t
r in
f in
t
OFF
t
dOFF
t
OFF state
ON state
OFF state
ON state
ON
t
output current
of a driver
50%
50%
80%
20%
20%
80%
50%
output current
of a driver
CSN low to high: data from shift register
is transferred to output power switches
t
CSN_HI,min
CSN
CLK
DI
DO
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
DI: data is not accepted
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
time
time
time
time
0
-
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Figure 12. PowerSO36 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.25
3.5
0.128
0.138
A2
3.3
0.13
A4
0.8
1
0.031
0.039
A5
0.2
0.008
a1
0
0.075
0
0.003
b
0.22
0.38
0.008
0.015
c
0.23
0.32
0.009
0.012
D
15.8
16
0.622
0.630
D1
9.4
9.8
0.37
0.38
D2
1
0.039
E
13.9
14.5
0.547
0.57
E1
10.9
11.1
0.429
0.437
E2
2.9
0.114
E3
5.8
6.2
0.228
0.244
E4
2.9
3.2
0.114
1.259
e
0.65
0.026
e3
11.05
0.435
G
0
0.075
0
0.003
H
15.5
15.9
0.61
0.625
h
1.1
0.043
L
0.8
1.1
0.031
0.043
N
10 (max)
s
8 (max)
Note: "D and E1" do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006")
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2
A
E
a1
PSO36MEC
DETAIL A
D
1
1
8
19
36
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
G
C
- C -
SEATING PLANE
e3
c
N
N
M
0.12
A B
b
B
A
H
E3
D1
BOTTOM VIEW
0096119 B
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Table 11. Revision History
Date
Revision
Description of Changes
April 2004
1
First Issue
June 2004
2
Changed Maturity from Product Preview to Final.
Changed values in the Table 4 ESD Protection.
July 2004
3
Small Change
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23/23
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