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Электронный компонент: LDO52

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June 2002
IP Library: High PSRR, Low Power,
70mA Low Dropout Voltage Regulator
s
DIGITAL BASEBAND REGULATOR
s
VERY LOW DROPOUT VOLTAGE : 50mV
s
HIGH PSRR : 60dB
s
LOW QUIESCENT CURRENT : 150
A
s
1
A STAND-BY MODE CURRENT
s
NO CURRENT IN POWER DOWN MODE
s
SHORT CIRCUIT PROTECTION
s
SMALL DECOUPLING CERAMIC CAPACITOR
APPLICATIONS
Cellular and Cordless phones supplied by 1 cell
Lithium-ion battery / 3 cells Ni-MH or Ni-Cd
battery.
PDA (Personal Digital Assistant), Smart phone.
Portable equipment.
Supply for Digital (Memory, DSP/Microcontroller)
devices.
APPLICATION NOTE
An external capacitor (C
OUT
= 1
F typical) with an
equivalent serial resistance (ESR) in the range
0.02 to 0.6
is used to ensure stability.
Figure 1 : Block Diagram
?
V
REF
?
?
?
LDO_52
OUT
IN
PWRDWN
STDBY
Figure 2 : Typical Application Circuit
1
F
ESR
V
OUT
C
OUT
?
?
OUT
GND
?
?
?
V
IN
IN
PWRDWN
Power Down Mode
OFF
ON
Stand-by Mode
STDBY
Active Mode
LDO_52

Stand-by Mode

LDO_52
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PRODUCT PREVIEW
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ELECTRICAL CHARACTERISTICS
3V < V
IN
< 5.5V, -30C < T < +125C, V
REF
= 2.8V, 0.8
F < C
OUT
< 1.2
F, 20m
< ESR < 0.6
.
100
A < I
LOAD
< 70mA.
Typical case : V
IN
= 4V, T = 25C, I
OUT
= 35mA.
Notes: 1. Above characteristics are given for 3V minimum input operating range voltage, but regulator is
operational with 2.7V minimum input voltage.
2. All parameters are guaranteed with 170mV Dropout voltage.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Voltage Range (Note 1)
V
IN
3
5,5
V
Output Voltage
V
OUT
2,8
V
Output Voltage Accuracy
-3
3
%
Output current
I
OUT
Active mode
70
mA
Low power mode
500
A
P
MOS
Output Resistance
R
ON
0,2
Dropout Voltage
V
DO
V
OUT
= 50mV,
I
LOAD
= 70mA
60
mV
(Note 2)
170
Quiescent current
I
Q
I
LOAD
= 100
A
20
30
A
I
LOAD
= 70mA
150
170
Stand-by current
I
STDBY
I
LOAD
= 500
A
5
10
A
Power down mode quiescent
current
I
QPRWDWN
Power down active
100
1000
nA
Power Supply Rejection Ratio
PSRR
DC
50
60
dB
f < 10KHz
40
45
Load Regulation
Ldr
V
OUT
= 2.8V
20
35
mV
Line Regulation
Lir
I
LOAD
= 70mA,
V
OUT
= 2.8V
2
3
mV
Std-by mode
I
LOAD
= 500
A
10
mV
Line Transient
Lirt
V
OUT
= 2.8V
I
LOAD
= 70mA,
V
IN
= 300mV,
t
RISE
= t
FALL
= 10
s
3
mV
Load Transient
Ldtr
10% to 90%
and 90% to 10%
of 70mA in 10
s
5
mV
Recovery time
5
6
s
Output decoupling capacitor
C
OUT
1
F
Settling time
(from power down to active mode)
V
OUT
= 2.8V,
C
OUT
= 1
F
20
50
s
Short Circuit Current Limit
I
SHORT
300
800
mA
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Figure 7 : Settling Time
TYPICAL CHARACTERISTICS
Figure 5 : Load transient
(I
LOAD
= 0 to 70mA ; V
BAT
= 4V)
Figure 6 : Load transient
(I
LOAD
= 0 to 70mA ; V
BAT
= 4V)
Figure 3 : Line transient
(I
LOAD
= 35mA ;
V
BAT
= 4V + 300mV with 10
s)
Figure 4 : Line transient
(I
LOAD
= 35mA ;
V
BAT
= 4V + 300mV with 10
s)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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LDO_52
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