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June 2002
IP Library: High PSRR, Very Low Power,
40mA Low Dropout Voltage Regulator
s
DIGITAL BASEBAND REGULATOR
s
VERY LOW DROPOUT VOLTAGE : 50mV
s
HIGH PSRR : 55dB
s
VERY LOW QUIESCENT CURRENT : 100
A
FULL LOAD
s
NO CURRENT IN POWER DOWN MODE
s
SHORT CIRCUIT PROTECTION
s
SMALL DECOUPLING CERAMIC CAPACITOR
TYPICAL APPLICATIONS
Cellular and Cordless phones supplied by 1 cell
Lithium-ion battery / 3 cells Ni-MH or Ni-Cd
battery.
PDA (Personal Digital Assistant), Smart phone.
Portable equipment
Supply for Digital (DSP/Microcontroller) devices.
APPLICATION NOTE
An external capacitor (C
OUT
= 1
F) with an
equivalent serial resistance (ESR) in the range
0.02 to 0.6
is used for regulator stability.
Figure 1 : Block Diagram
?
V
REF
?
?
LDO_53
OUT
IN
PWRDWN
Figure 2 : Typical Application Circuit
1
F
ESR
V
OUT
C
OUT
?
?
OUT
GND
?
?
V
IN
IN
Power Down Mode
OFF
ON
LDO_53
PWRDWN
LDO_53
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PRODUCT PREVIEW
LDO_53
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ELECTRICAL CHARACTERISTICS
3V < V
IN
< 5.5V, -30C < T < +85C, V
REF
= 2.8V, 0.8
F < C
OUT
< 1.2
F, 20m
< ESR < 0.6
.
100
A < I
LOAD
< 40mA.
Typical case : V
IN
= 4V, T = 25C, I
OUT
= 20mA.
Notes: 1. Above characteristics are given for 3V minimum input operating range voltage, but regulator is
operational with 2.7V minimum input voltage.
2. All parameters are guaranteed with 170mV Dropout voltage.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Voltage Range (Note 1)
V
IN
3
5,5
V
Output Voltage
V
OUT
2,8
V
Output Voltage Accuracy
-3
3
%
Output current
I
OUT
0,1
40
mA
P
MOS
Output Resistance
R
ON
0,4
Dropout Voltage
V
DO
V
OUT
= 50mV,
I
LOAD
= 40mA
50
mV
(Note 2)
170
Quiescent current
I
Q
I
LOAD
= 100
A
20
30
A
I
LOAD
= 40mA
100
120
Power down mode quiescent current
I
QPDN
Power down active
1
A
Power Supply Rejection Ratio
PSRR
DC
50
55
dB
f < 10KHz
45
50
Load Regulation
Ldr
15
25
mV
Line Regulation
Lir
I
LOAD
= 40mA,
V
IN
= 3V to 5.1V,
V
OUT
= 2.8V
2
3
mV
Line Transcient
Lirt
V
OUT
= 2.8V,
I
OUT
= 40mA,
V
IN
= 300mV
t
RISE
= t
FALL
= 10
s
3
mV
Load Transcient
Ldtr
V
OUT
= 2.8V,
t
RISE
= t
FALL
= 10
s
100
A < I
LOAD
< 40mA
3
mV
Recovery time
5
6
s
Output decoupling capacitor
C
OUT
1
F
Settling time
(from power down to active mode)
V
OUT
= 2.8V, C
OUT
= 1
F
20
50
s
Short Circuit Current Limit
I
SHORT
200
mA
LDO_53
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0
10
20
30
40
20
40
60
80
100
OUTPUT LOAD (mA)
CURR
E
N
T CO
MS
UMP
T
I
O
N
(
A
)
TYPICAL CHARACTERISTICS
Figure 7 : Load Transient - rising edge
(I
L
= 0 to 40 mA - V
IN
= 4V)
Figure 8 : Load Transient - falling edge
(I
L
= 40 to 0 mA - V
IN
= 4V)
Figure 5 : Line Transient - rising edge
(V
IN
= 4V + 300mV with 10
s)
Figure 6 : Line Transient - falling edge
(V
IN
= 4V + 300mV with 10
s)
Figure 3 : Quiescent Current vs Output Current
(I
L
= 0 to 40mA - V
IN
= 4V)
Figure 4 : Settling time
(V
IN
= 4V ; I
LOAD
= 20mA)
LDO_53
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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100
1000
10000
100000
30
40
50
60
70
Frequency (Hz)
PSRR
(
d
B)
Figure 9 : PSRR vs Frequency
(I
LOAD
max - V
IN
min)
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