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1/25
June 2005
M24128-BW, M24128-BR
M24256-BW, M24256-BR
256Kbit and 128Kbit Serial IC Bus EEPROM
With Three Chip Enable Lines
FEATURES SUMMARY
Compatible with I
2
C Extended Addressing
Two-Wire I
2
C Serial Interface
Supports 400kHz Protocol
Single Supply Voltage:
2.5 to 5.5V for M24128-BW, M24256-BW
1.8 to 5.5V for M24128-BR, M24256-BR
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
Table 1. Product List
Figure 1. Packages
Reference
Part Number
128 Kbits
M24128-BW
M24128-BR
256 Kbits
M24256-BW
M24256-BR
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
SO8 (MW)
200 mil width
8
1
M24128-BW, M24128-BR, M24256-BW, M24256-BR
2/25
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Operating Conditions (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. DC Characteristics (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. DC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. AC Characteristics ( M24128-BW, M24256-BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. AC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19
Table 16. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 19
Figure 13.SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 20
Table 17. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
20
Figure 14.SO8 wide 8 lead Plastic Small Outline, 200 mils body width, Package Outline . . . . . . 21
Table 18. SO8 wide 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
21
Figure 15.TSSOP8 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22
Table 19. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M24128-BW, M24128-BR, M24256-BW, M24256-BR
4/25
SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32K x 8 bits (M24256-BW and M24256-
BR) and 16K x 8 bits (M24128-BW and M24128-
BR).
Figure 2. Logic Diagram
Table 2. Signal Names
I
2
C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
Table 3.
), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master's 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset
In order to prevent inadvertent Write operations
during Power Up, a Power On Reset (POR) circuit
is implemented.
At Power Up, the device will not respond to any in-
struction until V
CC
has reached the POR threshold
voltage (this threshold is lower than the V
CC
mini-
mum operating voltage defined in
Table 8.
and
Ta-
ble 9.
). In the same way, as soon as V
CC
drops
from the normal operating voltage, below the POR
threshold voltage, all the operations are disabled
and the device will not respond to any instruction.
Prior to selecting and issuing instructions to the
memory, a valid and stable V
CC
voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (t
W
).
Figure 3. DIP, SO and TSSOP Connections
Note: See
PACKAGE MECHANICAL
section for package dimen-
sions, and how to identify pin-1.
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
AI02809
SDA
VCC
M24256-B
M24128-B
WC
SCL
VSS
3
E0-E2
SDA
VSS
SCL
WC
E1
E0
VCC
E2
AI02810B
M24256-B
M24128-B
1
2
3
4
8
7
6
5
5/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to V
CC
. (
Figure 4.
indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR'ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to V
CC
. (
Figure 4.
indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to V
CC
or V
SS
, to establish the Device Select
Code. When not connected (left floating), these in-
puts are read as Low (0,0,0).
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as V
IL
, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum R
P
Value versus Bus Parasitic Capacitance (C) for an I
2
C Bus
AI01665b
VCC
C
SDA
R
P
MASTER
R
P
SCL
C
100
0
4
8
12
16
20
C (pF)
Maximum RP value (k
)
10
1000
fc = 400kHz
fc = 100kHz