M24M01

2/19

SUMMARY DESCRIPTION
The M24M01 is a 1 Mbit (131,072 x 8) electrically
erasable programmable memory (EEPROM) ac-
cessed by an I

C-compatible bus.

Figure 2. Logic Diagram

Table 1. Signal Names

These devices are compatible with the I

C memo-

ry protocol. This is a two wire serial interface that
uses a bi-directional data bus and serial clock. The
devices carry a built-in 4-bit Device Type Identifier
code (1010) in accordance with the I

C bus defini-

tion.
The device behaves as a slave in the I

C protocol,

with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.

When writing data to the memory, the device in-
serts an acknowledge bit during the 9

bit time,

following the bus master's 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.

Figure 3. LGA Connections

Note: 1. DU = Don't Use (should be left unconnected, or tied to

)

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the POR

threshold value, and all operations are disabled
the device will not respond to any command. In the
same way, when V

drops from the operating

voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command. A stable and valid V

must be

applied before applying any logic signal.
When the power supply is turned on, V

rises

from V

to V

(min), passing through a value V

in between. The device ignores all instructions un-
til a time delay of t

has elapsed after the mo-

ment that V

rises above the V

threshold.

However, the correct operation of the device is not
guaranteed if, by this time, V

is still below

(min).No instructions should be sent until the

later of:
t

after V

passed the V

threshold

passed the V

(min) level

These values are specified in Table 9.

E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

Write Control

Supply Voltage

Ground

AI04048B

SDA

VCC

M24M01

SCL

VSS

E1-E2

SDA

VSS

SCL

VCC

AI04051C

M24M01

1
2
3
4

8
7
6
5

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M24M01

SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to V

. (Figure 4

indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR'ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V

. (Fig-

ure 4 indicates how the value of the pull-up resistor
can be calculated).

Chip Enable (E1, E2)
These input signals are used to set the value that
is to be looked for on bits b3 and b2 of the 7-bit De-
vice Select Code. These inputs must be tied to
V

or V

, to establish the Device Select Code.

When unconnected, the Chip Enable (E1, E2) sig-
nals are internally read as V

(see Tables 10 and

11).
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
ternally read as V

, and Write operations are al-

lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.

Figure 4. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL

CBUS

100

CBUS (pF)

Maximum RP value (k

)

1000

fc = 400kHz

fc = 100kHz

M24M01

4/19

DEVICE OPERATION
The device supports the I

C protocol. This is sum-

marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24M01 device is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the
eight data bits.

Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change

only

when Serial Clock (SCL) is driv-

en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 2-bit Chip Enable "Address"
(E1, E2). To address the memory array, the 4-bit
Device Type Identifier is 1010b.
Up to four memory devices can be connected on a
single I

C bus. Each one is given a unique 2-bit

code on the Chip Enable (E1, E2) inputs. When
the Device Select Code is received on Serial Data
(SDA), the device only responds if the Chip Enable
Address is the same as the value on the Chip En-
able (E1, E2) inputs.
The 8

bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9

bit time. If the

device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.

Table 2. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier

Chip Enable Address

Device Select Code

A16

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M24M01

Figure 5. I

C Bus Protocol

Table 3. Operating Modes

Note: 1. X =

or V

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

START, Device Select, RW = 1

Random Address Read

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Sequential Read

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

128

START, Device Select, RW = 0

SCL

SDA

SCL

SDA

START

Condition

SDA

Input

SDA

Change

AI00792B

STOP

Condition

MSB

ACK

START

Condition

SCL

MSB

ACK

STOP

Condition

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