1/9
NOT FOR NEW DESIGN
November 2000
This is information on a product still in production but not recommended for new designs.
M2716
NMOS 16 Kbit (2Kb x 8) UV EPROM
s
2048 x 8 ORGANIZATION
s
525mW Max ACTIVE POWER, 132mW Max
STANDBY POWER
s
ACCESS TIME:
M2716-1 is 350ns
M2716 is 450ns
s
SINGLE 5V SUPPLY VOLTAGE
s
STATIC-NO CLOCKS REQUIRED
s
INPUTS and OUTPUTS TTL COMPATIBLE
DURING BOTH READ and PROGRAM
MODES
s
THREE-STATE OUTPUT with TIED-OR-
CAPABILITY
s
EXTENDED TEMPERATURE RANGE
s
PROGRAMMING VOLTAGE: 25V
DESCRIPTION
The M2716 is a 16,384 bit UV erasable and elec-
trically programmable memory EPROM, ideally
suited for applications where fast turn around and
pattern experimentation are important require-
ments.
The M2716 is housed in a 24 pin Window Ceramic
Frit-Seal Dual-in-Line package. The transparent
lid allows the user to expose the chip to ultraviolet
light to erase the bit pattern. A new pattern can
then be written to the device by following the pro-
gramming procedure.
Figure 1. Logic Diagram
AI00784B
11
A0-A10
Q0-Q7
VCC
M2716
G
EP
VSS
8
VPP
1
24
FDIP24W (F)
Q2
VSS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
EP
Q3
VPP
Q7
Q6
Q4
A4
VCC
A7
AI00785
M2716
8
1
2
3
4
5
6
7
9
10
11
12
20
19
18
17
16
15
A6
A5
A9
A8
23
22
21
14
13
24
Figure 2. DIP Pin Connections
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
grade 1
grade 6
0 to 70
40 to 85
C
T
BIAS
Temperature Under Bias
grade 1
grade 6
10 to 80
50 to 95
C
T
STG
Storage Temperature
65 to 125
C
V
CC
Supply Voltage
0.3 to 6
V
V
IO
Input or Output Voltages
0.3 to 6
V
V
PP
Program Supply
0.3 to 26.5
V
P
D
Power Dissipation
1.5
W
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for ex tended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
DEVICE OPERATION
The M2716 has 3 modes of operation in the normal
system environment. These are shown in Table 3.
Read Mode. The M2716 read operation requires
that G = V
IL
, EP = V
IL
and that addresses A0-A10
have been stabilized. Valid data will appear on the
output pins after time t
AVQV
, t
GLQV
or t
ELQV
(see
Switching Time Waveforms) depending on which is
limiting.
Deselect Mode. The M2716 is deselected by mak-
ing G = V
IH
. This mode is independent of EP and
the condition of the addresses. The outputs are
Hi-Z when G = V
IH
. This allows tied-OR of 2 or more
M2716's for memory expansion.
Standby Mode (Power Down). The M2716 may
be powered down to the standby mode by making
EP = V
IH
. This is independent of G and automat-
ically puts the outputs in the Hi-Z state. The power
is reduced to 25% (132 mW max) of the normal
operating power. V
CC
and V
PP
must be maintained
at 5V. Access time at power up remains either t
AVQV
or t
ELQV
(see Switching Time Waveforms).
Programming
The M2716 is shipped from SGS-THOMSON com-
pletely erased. All bits will be at "1" level (output
high) in this initial state and after any full erasure.
Table 3 shows the 3 programming modes.
Program Mode. The M2716 is programmed by
introducing "0"s into the desired locations. This is
done 8 bits (a byte) at a time. Any individual address,
sequential addresses, or addresses chosen at ran-
dom may be programmed. Any or all of the 8 bits
associated with an address location may be pro-
grammed with a single program pulse applied to the
EP pin. All input voltage levels including the program
pulse on chip enable are TTL compatible.
The programming sequence is: with V
PP
= 25V, V
CC
= 5V, G = V
IH
and EP = V
IL
, an address is selected
and the desired data word is applied to the output
pins (V
IL
= "0" and V
IH
= "1" for both address and
data). After the address and data signals are stable
the program pin is pulsed from V
IL
to V
IH
with a
M2716
2/9
pulse width between 45ms and 55ms. Multiple
pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(V
IH
or higher) must not be maintained longer than
t
PHPL
(max) on the program pin during program-
ming. M2716's may be programmed in parallel in
this mode.
Program Verify Mode. The programming of the
M2716 may be verified either one byte at a time
during the programming (as shown in Figure 6) or
by reading all of the bytes out at the end of the
programming sequence. This can be done with
V
PP
= 25V or 5V in either case. V
PP
must be at 5V
for all operating modes and can be maintained at
25V for all programming modes.
Program Inhibit Mode. The program inhibit mode
allows several M2716's to be programmed simul-
taneously with different data for each one by con-
trolling which ones receive the program pulse. All
similar inputs of the M2716 may be paralleled.
Pulsing the program pin (from V
IL
to V
IH
) will pro-
gram a unit while inhibiting the program pulse to a
unit will keep it from being programmed and keep-
ing G = V
IH
will put its outputs in the Hi-Z state.
ERASURE OPERATION
The M2716 is erased by exposure to high intensity
ultraviolet light through the transparent window.
This exposure discharges the floating gate to its
initial state through induced photo current. It is
recommended that the M2716 be kept out of direct
sunlight. The UV content of sunlight may cause
a partial erasure of some bits in a relatively short
period of time.
An ultraviolet source of 2537 yielding a total
integrated dosage of 15 watt-seconds/cm
2
power
rating is used. The M2716 to be erased should be
placed 1 inch away from the lamp and no filters
should be used.
An erasure system should be calibrated peri-
odically. The erasure time is increased by the
square of the distance (if the distance is doubled
the erasure time goes up by a factor of 4). Lamps
lose intensity as they age, it is therefore important
to periodically check that the UV system is in good
order.
This will ensure that the EPROMs are being com-
pletely erased. Incomplete erasure will cause
symptoms that can be misleading. Programmers,
components, and system designs have been erro-
neously suspected when incomplete erasure was
the basic problem.
DEVICE OPERATION (cont'd)
Mode
EP
G
V
PP
Q0 - Q7
Read
V
IL
V
IL
V
CC
Data Out
Program
V
IH
Pulse
V
IH
V
PP
Data In
Verify
V
IL
V
IL
V
PP
or V
CC
Data Out
Program Inhibit
V
IL
V
IH
V
PP
Hi-Z
Deselect
X
V
IH
V
CC
Hi-Z
Standby
V
IH
X
V
CC
Hi-Z
Note: X = V
IH
or V
IL
.
Table 3. Operating Modes
M2716
3/9
AI00827
2.4V
0.45V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveforms
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.45V to 2.4V
Input and Output Timing Ref. Voltages
0.8V to 2.0V
AC MEASUREMENT CONDITIONS
AI00828
1.3V
OUT
CL = 100pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 4. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= V
CC
, EP = V
CC
10
A
I
CC
Supply Current
EP = V
IL
, G = V
IL
100
mA
I
CC1
Supply Current (Standby)
EP = V
IH
, G = V
IL
25
mA
I
PP
Program Current
V
PP
= V
CC
5
mA
V
IL
Input Low Voltage
0.1
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.45
V
V
OH
Output High Voltage
I
OH
= 400
A
2.4
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 5. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
M2716
4/9
AI00786
tAXQX
tEHQZ
DATA OUT
A0-A10
EP
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
Figure 5. Read Mode AC Waveforms
Symbol
Alt
Parameter
Test Condition
M2716
Unit
-1
blank
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
EP = V
IL
, G = V
IL
350
450
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
350
450
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
EP = V
IL
120
120
ns
t
EHQZ
(2)
t
OD
Chip Enable High to Output Hi-Z
G = V
IL
0
100
0
100
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
EP = V
IL
0
100
0
100
ns
t
AXQX
t
OH
Address Transition to Output Transition
EP = V
IL
, G = V
IL
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Table 6. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
V
IL
V
IN
V
IH
10
A
I
CC
Supply Current
100
mA
I
PP
Program Current
5
mA
I
PP1
Program Current Pulse
EP = V
IH
Pulse
30
mA
V
IL
Input Low Voltage
0.1
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 1
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 7. Programming Mode DC Characteristics
(1)
(T
A
= 25
C; V
CC
= 5V
5%; V
PP
= 25V
1V)
M2716
5/9
PDF 
ZIP