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Электронный компонент: M27C202-100N6TR

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1/15
April 1999
M27C202
2 Mbit (128Kb x16) UV EPROM and OTP EPROM
s
5V
10% SUPPLY VOLTAGE in READ
OPERATION
s
ACCESS TIME: 45ns
s
LOW POWER CONSUMPTION:
Active Current 50mA at 5MHz
Standby Current 100
A
s
PROGRAMMING VOLTAGE: 12.75V
0.25V
s
PROGRAMMING TIME: 100
s/word
s
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code: 1Ch
DESCRIPTION
The M27C202 is a 2 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs, in
the application where the contents is stable and
needs to be programmed only one time, and is or-
ganised as 131,072 by 16 bits.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C202 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
Figure 1. Logic Diagram
AI01815
17
A0-A16
P
Q0-Q15
VPP
VCC
M27C202
G
E
VSS
16
1
40
1
40
FDIP40W (F)
PDIP40 (B)
PLCC44 (K)
TSOP40 (N)
10 x 14 mm
M27C202
2/15
Figure 2B. TSOP Connections
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A8
A11
A10
A4
A15
A9
G
A7
A2
DQ1
DQ0
A0
A1
A3
A16
P
E
DQ14
VPP
VCC
DQ15
AI01817B
M27C202
10
1
11
20
21
30
31
40
VSS
A12
A6
A13
A5
DQ12
DQ4
DQ11
DQ5
VSS
Figure 2A. DIP Connections
Q6
Q5
Q4
Q11
Q8
VSS
Q7
Q10
Q9
A12
A8
A11
A10
A6
A13
A9
VSS
A7
A2
Q1
Q0
A0
G
A1
A5
A16
P
E
Q12
VPP
VCC
Q15
AI02784
M27C202
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q3
Q2
Q14
Q13
A4
A3
40
39
38
37
36
35
34
33
A14
A15
Figure 2C. LCC Connections
AI01816
A14
A11
A7
A3
23
Q6
Q5
Q4
Q3
Q2
NC
A2
Q12
Q8
VSS
NC
Q11
Q10
12
A15
A9
1
Q15
VSS
A12
Q13
A5
44
NC
A16
M27C202
Q14
A13
A4
NC
A6
34
Q1
Q9
A10
A8
Q7
Q0
G
A0
A1
V
PP
E
P
V
CC
Table 1. Signal Names
A0-A16
Address Inputs
Q0-Q15
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
3/15
M27C202
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V
0.5V.
Table 4. Electronic Signature
Note: Outputs Q15-Q8 are set to '0'.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
G
P
A9
V
PP
Q15-Q0
Read
V
IL
V
IL
V
IH
X
V
CC
or V
SS
Data Output
Output Disable
V
IL
V
IH
X
X
V
CC
or V
SS
Hi-Z
Program
V
IL
X
V
IL
Pulse
X
V
PP
Data Input
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Output
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
or V
SS
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
0
0
1
1
1
0
0
1Ch
M27C202
4/15
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condit ion
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
DEVICE OPERATION
The operating modes of the M27C202 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27C202 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
OE
from the falling edge of G, assuming that E
has been low and the addresses have been stable
for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C202 has a standby mode which reduces
the supply current from 50mA to 100
A.
The M27C202 is placed in the standby mode by
applying a TTL high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
5/15
M27C202
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C, 40 to 85
C or 40 to 125
C; V
CC
= 5V
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V
100
A
I
PP
Program Current
V
PP
= V
CC
100
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
A
2.4
V
Output High Voltage CMOS
I
OH
= 100
A
V
CC
0.7V
V
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1
F ceram-
ic capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7
F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
M27C202
6/15
Table 8. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C, 40 to 85
C or 40 to 125
C; V
CC
= 5V
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Symbol
Alt
Parameter
Test Condition
M27C202
Unit
-45
(3)
-70
(3)
-80
-100
Min
Max
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
45
70
80
100
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
45
70
80
100
ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
25
40
40
50
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
25
0
30
0
30
0
30
ns
t
GHQZ
(2)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0
25
0
30
0
30
0
30
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
0
0
ns
Figure 5. Read Mode AC Waveforms
AI01818B
tAXQX
tEHQZ
A0-A16
E
G
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
7/15
M27C202
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
IH
10
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
A
2.4
V
V
ID
A9 Voltage
11.5
12.5
V
Symbol
Alt
Parameter
Test Condi tion
Min
Max
Unit
t
AVPL
t
AS
Address Valid to Program Low
2
s
t
QVPL
t
DS
Input Valid to Program Low
2
s
t
VPHPL
t
VPS
V
PP
High to Program Low
2
s
t
VCHPL
t
VCS
V
CC
High to Program Low
2
s
t
ELPL
t
CES
Chip Enable Low to Program Low
2
s
t
PLPH
t
PW
Program Pulse Width
95
105
s
t
PHQX
t
DH
Program High to Input Transition
2
s
t
QXGL
t
OES
Input Transition to Output Enable Low
2
s
t
GLQV
t
OE
Output Enable Low to Output Valid
100
ns
t
GHQZ
(2)
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address
Transition
0
ns
Programming
When delivered (and after each `1's erasure for UV
EPROM), all bits of the M27C202 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a `0' to a `1' is by die exposure to ultraviolet
light (UV EPROM). The M27C202 is in the pro-
gramming mode when V
PP
input is at 12.75V, E is
at V
IL
and P is pulsed to V
IL
. The data to be pro-
grammed is applied to 16 bits in parallel, to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. V
CC
is specified to
be 6.25V
0.25V.
M27C202
8/15
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00706
A0-A15
Q0-Q15
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 7. Programming Flowchart
AI00707C
n = 0
Last
Addr
VERIFY
P = 100
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100
s program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C202s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C202 may be common. A TTL low level pulse
applied to a M27C202's P input, with E low and
V
PP
at 12.75V, will program that M27C202. A high
level E input inhibits the other M27C202s from be-
ing programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
9/15
M27C202
On-Board Programming
The M27C202 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25
C
5
C am-
bient temperature range that is required when pro-
gramming the M27C202. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the M27C202
with V
PP
= V
CC
= 5V. Two identifier bytes may
then be sequenced from the device outputs by tog-
gling address line A0 from V
IL
to V
IH
. All other ad-
dress lines must be held at V
IL
during Electronic
Signature mode. Byte 0 (A0 = V
IL
) represents the
manufacturer code and byte 1 (A0 = V
IH
) the de-
vice identifier code. For the STMicroelectronics
M27C202, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q7 to Q0.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27C202 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 . It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C202 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C202 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27C202 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27C202 is exposure to short wave ultraviolet
light which has wavelength 2537 . The integrated
dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm
2
. The era-
sure time with this dosage is approximately 15 to
20 minutes
using an
ultraviolet
lamp
with
12000
W/cm
2
power rating. The M27C202 should
be placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before era-
sure.
M27C202
10/15
Table 11. Ordering Information Scheme
Note: 1. High Speed, see AC Characteristics section for further information.
2. These speeds are replaced by the 100ns.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Example:
M27C202
-80
K
1
TR
Device Type
M27
Supp ly Voltage
C = 5V
10%
Device Function
202 = 2 Mbit (128Kb x16)
Speed
-45
(1)
= 45 ns
-70
(1)
= 70 ns
-80 = 80 ns
-100 = 100 ns
Not For New Design
(2)
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP40W
B = PDIP40
K = PLCC44
N = TSOP40: 10 x 14 mm
Temperature Range
1 = 0 to 70
C
3 = 40 to 125
C
6 = 40 to 85
C
Optio ns
TR = Tape & Reel Packing
11/15
M27C202
Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
5.72
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
51.79
52.60
2.039
2.071
D2
48.26
1.900
E
15.24
0.600
E1
13.06
13.36
0.514
0.526
e
2.54
0.100
eA
14.99
0.590
eB
16.18
18.03
0.637
0.710
L
3.18
0.125
S
1.52
2.49
0.060
0.098
8.13
0.320
4
11
4
11
N
40
40
Figure 8. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline
Drawing is not to scale.
FDIPW-a
A3
A1
A
L
B1
B
e
D
S
E1
E
N
1
C
eA
D2
eB
A2
M27C202
12/15
Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
4.45
0.175
A1
0.64
0.38
0.025
0.015
A2
3.56
3.91
0.140
0.154
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
51.78
52.58
2.039
2.070
D2
48.26
1.900
E
14.80
16.26
0.583
0.640
E1
13.46
13.99
0.530
0.551
e1
2.54
0.100
eA
15.24
0.600
eB
15.24
17.78
0.600
0.700
L
3.05
3.81
0.120
0.150
S
1.52
2.29
0.060
0.090
0
15
0
15
N
40
40
Figure 9. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline
Drawing is not to scale.
PDIP
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
eB
D2
13/15
M27C202
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
4.20
4.70
0.165
0.185
A1
2.29
3.04
0.090
0.120
A2
0.51
0.020
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
17.40
17.65
0.685
0.695
D1
16.51
16.66
0.650
0.656
D2
14.99
16.00
0.590
0.630
E
17.40
17.65
0.685
0.695
E1
16.51
16.66
0.650
0.656
E2
14.99
16.00
0.590
0.630
e
1.27
0.050
F
0.00
0.25
0.000
0.010
R
0.89
0.035
N
44
44
CP
0.10
0.004
Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
Drawing is not to scale.
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
M27C202
14/15
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.80
14.20
0.543
0.559
D1
12.30
12.50
0.484
0.492
E
9.90
10.10
0.390
0.398
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
5
0
5
N
40
40
CP
0.10
0.004
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1
15/15
M27C202
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