1/15
November 2000
M27C320
32 Mbit (4Mb x8 or 2Mb x16) OTP EPROM
s
5V 10% SUPPLY VOLTAGE in READ
OPERATION
s
ACCESS TIME: 80ns
s
BYTE-WIDE or WORD-WIDE
CONFIGURABLE
s
32 Mbit MASK ROM REPLACEMENT
s
LOW POWER CONSUMPTION
Active Current 70mA at 8MHz
Stand-by Current 100mA
s
PROGRAMMING VOLTAGE: 12V 0.25V
s
PROGRAMMING TIME: 50s/word
s
ELECTRONIC SIGNATURE:
Manufacturer Code 20h
Device Code: 32h
DESCRIPTION
The M27C320 is a 32 Mbit EPROM offered in the
OTP range (one time programmable). It is ideally
suited for microprocessor systems requiring large
data or program storage. It is organised as either
4 MWords of 8 bit or 2 MWords of 16 bit. The pin-
out is compatible with the 32 Mbit Mask ROM.
The M27C320 is offered in SO44 and TSOP48
(12 x 20 mm) packages.
44
1
SO44 (M)
TSOP48 (N)
12 x 20 mm
Figure 1. Logic Diagram
AI02152
21
A0-A20
GVPP
Q0-Q14
VCC
M27C320
BYTE
E
VSS
15
Q15A1
M27C320
2/15
Figure 2B. TSOP Connections
AI02154
M27C320
12
1
13
24
25
36
37
48
GVPP
Q0
Q8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
Q7
A12
A16
BYTE
Q15A1
Q5
Q2
Q3
VCC
Q11
Q4
Q14
A9
A19
A18
A4
A20
A7
Q1
Q9
A6
A5
Q6
Q13
A11
A10
Q10
Q12
A17
A8
VSS
VCC
VSS
VSS
VSS
Figure 2A. SO Connections
GVPP
Q0
Q8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
Q7
A12
A16
BYTE
Q15A1
Q5
Q2
Q3
VCC
Q11
Q4
Q14
A9
A19
A18
A4
NC
A20
A7
AI02153
M27C320
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
Q1
Q9
A6
A5
Q6
Q13
44
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
43
1
42
41
A17
A8
Table 1. Signal Names
A0-A20
Address Inputs
Q0-Q7
Data Outputs
Q8-Q14
Data Outputs
Q15A1
Data Output / Address Input
E
Chip Enable
GV
PP
Output Enable / Program Supply
BYTE
Byte-Wide Select
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
DEVICE OPERATION
The operating modes of the M27C320 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C320 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTE pin. When BYTE is at V
IH
the Word-wide organisation is selected and the
Q15A1 pin is used for Q15 Data Output. When
the BYTE pin is at V
IL
the Byte-wide organisation
is selected and the Q15A1 pin is used for the Ad-
dress Input A1. When the memory is logically re-
garded as 16 bit wide, but read in the Byte-wide
organisation, then with A1 at V
IL
the lower 8 bits
of the 16 bit data are selected and with A1 at V
IH
the upper 8 bits of the 16 bit data are selected.
3/15
M27C320
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V 0.5V.
Table 4. Electronic Signature
Note: Outputs Q15-Q8 are set to '0'.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
GV
PP
BYTE
A9
Q15A1
Q14-Q8
Q7-Q0
Read Word-wide
V
IL
V
IL
V
IH
X
Data Out
Data Out
Data Out
Read Byte-wide Upper
V
IL
V
IL
V
IL
X
V
IH
Hi-Z
Data Out
Read Byte-wide Lower
V
IL
V
IL
V
IL
X
V
IL
Hi-Z
Data Out
Output Disable
V
IL
V
IH
X
X
Hi-Z
Hi-Z
Hi-Z
Program
V
IL
Pulse
V
PP
V
IH
X
Data In
Data In
Data In
Program Inhibit
V
IH
V
PP
V
IH
X
Hi-Z
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Hi-Z
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
Code
Codes
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
0
1
1
0
0
1
0
32h
M27C320
4/15
The M27C320 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C320 has standby mode which reduces
the supply current from 50mA to 100A. The
M27C320 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25 C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
5/15
M27C320
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 C, 40 to 85 C or 40 to 125 C; V
CC
= 5V 10%)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 8MHz
70
mA
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz
50
mA
I
CC
1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC
2
Supply Current (Standby) CMOS
E > V
CC
0.2V
100
A
I
PP
Program Current
V
PP
= V
CC
10
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400A
2.4
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
that a 0.1F ceramic capacitor is used on every
device between V
CC
and V
SS
. This should be a
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7F electrolytic capacitor
should be used between V
CC
and V
SS
for every
eight devices. This capacitor should be mounted
near the power supply connection point. The pur-
pose of this capacitor is to overcome the voltage
drop caused by the inductive effects of PCB trac-
es.
M27C320
6/15
Figure 5. Word-Wide Read Mode AC Waveforms
Note: BYTE = V
IH
.
AI02207
tAXQX
tEHQZ
A0-A20
E
GVPP
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table 8. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 C, 40 to 85 C or 40 to 125 C; V
CC
= 5V 10%)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Symbol
Alt
Parameter
Test Condition
M27C320
Unit
-80
(3)
-100
-120
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output
Valid
E = V
IL
, G = V
IL
80
100
120
ns
t
BHQV
t
ST
BYTE High to Output Valid
E = V
IL
, G = V
IL
80
100
120
ns
t
ELQV
t
CE
Chip Enable Low to Output
Valid
G = V
IL
80
100
120
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
40
50
60
ns
t
BLQZ
(2)
t
STD
BYTE Low to Output Hi-Z
E = V
IL
, G = V
IL
40
40
50
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output
Hi-Z
G = V
IL
0
40
0
40
0
50
ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
40
0
40
0
50
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
5
5
5
ns
t
BLQX
t
OH
BYTE Low to Output
Transition
E = V
IL
, G = V
IL
5
5
5
ns
7/15
M27C320
Figure 6. Byte-Wide Read Mode AC Waveforms
Note: BYTE = V
IL
.
Figure 7. BYTE Transition AC Waveforms
Note: E = V
IL
; GV
PP
= V
IL
.
AI02218
tAXQX
tEHQZ
A0-A20
E
GVPP
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
AI02219
tAXQX
tBHQV
A0-A20
BYTE
tAVQV
tBLQX
tBLQZ
VALID
Hi-Z
A1
DATA OUT
DATA OUT
VALID
Q0-Q7
Q8-Q15
M27C320
8/15
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25 C; V
CC
= 6.25V 0.25V; V
PP
= 12V 0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. MARGIN MODE AC Characteristics
(1)
(T
A
= 25 C; V
CC
= 6.25V 0.25V; V
PP
= 12V 0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
V
IL
V
IN
V
IH
10
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.4
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 2.5mA
3.5
V
V
ID
A9 Voltage
11.5
12.5
V
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
A9HVPH
t
AS9
V
A9
High to V
PP
High
2
s
t
VPHEL
t
VPS
V
PP
High to Chip Enable Low
2
s
t
A10HEH
t
AS10
V
A10
High to Chip Enable High (Set)
1
s
t
A10LEH
t
AS10
V
A10
Low to Chip Enable High (Reset)
1
s
t
EXA10X
t
AH10
Chip Enable Transition to V
A10
Transition
1
s
t
EXVPX
t
VPH
Chip Enable Transition to V
PP
Transition
2
s
t
VPXA9X
t
AH9
V
PP
Transition to V
A9
Transition
2
s
Programming
When delivered, all bits of the M27C320 are in the
'1' state. Data is introduced by selectively pro-
gramming '0's into the desired bit locations. Al-
though only '0's will be programmed, both '1's and
'0's can be present in the data word. The
M27C320 is in the programming mode when V
PP
input is at 12.5V, G is at V
IH
and E is pulsed to V
IL
.
The data to be programmed is applied to 16 bits in
parallel to the data output pins. The levels required
for the address and data inputs are TTL. V
CC
is
specified to be 6.25V 0.25V.
9/15
M27C320
Table 11. Programming Mode AC Characteristics
(1)
(T
A
= 25 C; V
CC
= 6.25V 0.25V; V
PP
= 12V 0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
1
s
t
QVEL
t
DS
Input Valid to Chip Enable Low
1
s
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
2
s
t
VPHEL
t
OES
V
PP
High to Chip Enable Low
1
s
t
VPLVPH
t
PRT
V
PP
Rise Time
50
ns
t
ELEH
t
PW
Chip Enable Program Pulse Width (Initial)
45
55
s
t
EHQX
t
DH
Chip Enable High to Input Transition
2
s
t
EHVPX
t
OEH
Chip Enable High to V
PP
Transition
2
s
t
VPLEL
t
VR
V
PP
Low to Chip Enable Low
1
s
t
ELQV
t
DV
Chip Enable Low to Output Valid
1
s
t
EHQZ
(2)
t
DFP
Chip Enable High to Output Hi-Z
0
130
ns
t
EHAX
t
AH
Chip Enable High to Address Transition
0
ns
Figure 8. MARGIN MODE AC Waveforms
Note: A8 High level = 5V; A9 High level = 12V.
AI00736B
tA9HVPH
tVPXA9X
A8
E
GVPP
A10 Set
VCC
tVPHEL
tA10LEH
tEXVPX
tA10HEH
A9
A10 Reset
tEXA10X
M27C320
10/15
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 100 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50s program pulses to each word
until a correct verify occurs (see Figure 10). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27C320s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C320 may be common. A TTL low level pulse
applied to a M27C320's E input and V
PP
at 12V,
will program that M27C320. A high level E input in-
hibits the other M27C320s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V
IL
. Data should be verified with t
ELQV
after the
falling edge of E.
Figure 9. Programming and Verify Modes AC Waveforms
Note: BYTE = V
IH
; GV
PP
High level = 12V.
tAVEL
VALID
AI02205
A0-A20
Q0-Q15
VCC
DATA IN
DATA OUT
E
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHVPX
tELQV
tELEH
tEHQZ
tVPLEL
PROGRAM
VERIFY
GVPP
tEHAX
Figure 10. Programming Flowchart
AI02220
n = 0
Last
Addr
VERIFY
E = 50
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12V
FAIL
CHECK ALL WORDS
BYTE = VIH
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
SET MARGIN MODE
RESET MARGIN MODE
11/15
M27C320
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25C 5C am-
bient temperature range that is required when pro-
gramming the M27C320. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C320, with V
PP
= V
CC
= 5V. Two identifier
bytes may then be sequenced from the device out-
puts by toggling address line A0 from V
IL
to V
IH
. All
other address lines must be held at V
IL
during
Electronic Signature mode.
Byte 0 (A0 = V
IL
) represents the manufacturer
code and byte 1 (A0 = V
IH
) the device identifier
code. For the STMicroelectronics M27C320, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q7 to Q0.
M27C320
12/15
Table 12. Ordering Information Scheme
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Example:
M27C320
-80 M
1
Device Type
M27
Supply Voltage
C = 5V 10%
Device Function
320 = 32 Mbit (4Mb x 8 or 2Mb x 16)
Speed
-80
(1)
= 80 ns
-100 = 100 ns
-120 = 120 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 C
6 = 40 to 85 C
3 = 40 to 125 C
Table 13. Revision History
Date
Revision Details
September 1998
First Issue
09/20/00
AN620 Reference removed
11/29/00
From Preliminary Data to data Sheet
40 to 85 C and 40 to 125 C temperature ranges added (Tables 7, 8 and 12)
80ns speed class in High Speed AC measurement conditions (Tables 8 and 12)
Note changed (Figures 6 and 9)
Programming Flowchart change (Figure 10)
Presto III Programming Algorithm paragraph changed
13/15
M27C320
Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
2.42
2.62
0.095
0.103
A1
0.22
0.23
0.009
0.010
A2
2.25
2.35
0.089
0.093
B
0.50
0.020
C
0.10
0.25
0.004
0.010
D
28.10
28.30
1.106
1.114
E
13.20
13.40
0.520
0.528
e
1.27
0.050
H
15.90
16.10
0.626
0.634
L
0.80
0.031
3
3
N
44
44
CP
0.10
0.004
Figure 11. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
Drawing is not to scale.
SO-b
E
N
CP
B
e
A2
D
C
L
A1
H
A
1
M27C320
14/15
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1
Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
11.90
12.10
0.469
0.476
e
0.50
-
-
0.020
-
-
L
0.50
0.70
0.020
0.028
0
5
0
5
N
48
48
CP
0.10
0.004
15/15
M27C320
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