1/14

May 1999

M27C400

4 Mbit (512Kb x8 or 256Kb x16) UV EPROM and OTP EPROM

5V ± 10% SUPPLY VOLTAGE in READ
OPERATION

ACCESS TIME: 55ns

BYTE-WIDE or WORD-WIDE
CONFIGURABLE

4 Mbit MASK ROM REPLACEMENT

LOW POWER CONSUMPTION

Active Current 70mA at 8MHz

Stand-by Current 100µA

PROGRAMMING VOLTAGE: 12.5V ± 0.25V

PROGRAMMING TIME: 100µs/word

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: B8h

DESCRIPTION
The M27C400 is an 4 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage. It is organised as either 512 Kwords of 8
bit or 256 Kwords of 16 bit. The pin-out is compat-
ible with the most common 8 Mbit Mask ROM.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern.
A new pattern can then be written rapidly to the de-
vice by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C400 is offered in PDIP40 package.

FDIP40W (F)

PDIP40 (B)

Figure 1. Logic Diagram

AI01634

A0-A17

BYTEVPP

Q0-Q14

VCC

M27C400

VSS

Q15A1

M27C400

2/14

Figure 2. DIP Connections

Q11

VSS

A14

Q15A1

A15

A16

Q14

A13

BYTEVPP
VSS

Q12

Q10

VCC

A10

A17

AI01635

M27C400

Q13

A12

A11

Table 1. Signal Names

A0-A17

Address Inputs

Q0-Q7

Data Outputs

Q8-Q14

Data Outputs

Q15A1

Data Output / Address Input

Chip Enable

Output Enable

BYTEV

Byte Mode / Program Supply

Supply Voltage

Ground

DEVICE OPERATION
The operating modes of the M27C400 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V

and 12V on A9 for the

Electronic Signature.
Read Mode
The M27C400 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV

pin. When BYTEV

is at V

the Word-wide organisation is selected

and the Q15A1 pin is used for Q15 Data Output.
When the BYTEV

pin is at V

the Byte-wide or-

ganisation is selected and the Q15A1 pin is used
for the Address Input A1. When the memory is

logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A1 at V

the

lower 8 bits of the 16 bit data are selected and with
A1 at V

the upper 8 bits of the 16 bit data are

selected.

The M27C400 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t

AVQV

) is equal to the delay

from E to output (t

ELQV

). Data is available at the

output after a delay of t

GLQV

from the falling edge

of G, assuming that E has been low and the ad-
dresses have been stable for at least t

AVQV

-t

GLQV

Standby Mode
The M27C400 has a standby mode which reduces
the supply current from 50mA to 100µA. The
M27C400 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.

3/14

M27C400

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = V

or V

, V

= 12V ± 0.5V.

Table 4. Electronic Signature

Note: Outputs Q15-Q8 are set to '0'.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 125

°C

BIAS

Temperature Under Bias

50 to 125

°C

STG

Storage Temperature

65 to 150

°C

(2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

(2)

A9 Voltage

2 to 13.5

Program Supply Voltage

2 to 14

Mode

BYTEV

Q7-Q0

Q14-Q8

Q15A1

Read Word-wide

Data Out

Read Byte-wide Upper

Data Out

Hi-Z

Read Byte-wide Lower

Data Out

Hi-Z

Output Disable

Hi-Z

Program

Pulse

Data In

Verify

Data Out

Program Inhibit

Hi-Z

Standby

Hi-Z

Electronic Signature

Codes

Code

Identifier

Hex Data

Manufacturer's Code

20h

Device Code

B2h

M27C400

4/14

Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2-line con-
trol function which accommodates the use of mul-
tiple memory connection. The two-line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

Table 5. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Figure 3. Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

3.3k

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance

(1)

= 25 °C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance (except BYTEV

)

= 0V

Input Capacitance (BYTEV

)

= 0V

120

OUT

Output Capacitance

OUT

= 0V

5/14

M27C400

Table 7. Read Mode DC Characteristics

(1)

= 0 to 70 °C or 40 to 85 °C; V

= 5V ± 5% or 5V ± 10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

±1

µA

Output Leakage Current

OUT

±10

µA

Supply Current

E = V

, G = V

OUT

= 0mA, f = 8MHz

E = V

, G = V

OUT

= 0mA, f = 5MHz

CC1

Supply Current (Standby) TTL

E = V

CC2

Supply Current (Standby) CMOS

E > V

0.2V

100

µA

Program Current

= V

µA

Input Low Voltage

0.3

0.8

(2)

Input High Voltage

+ 1

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400µA

2.4

System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I

has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between V

and V

. This should be a high frequency type of

low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween V

and V

for every eight devices. This

capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C400 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposition to ultravio-
let light (UVEPROM). The M27C400 is in the pro-
gramming mode when V

input is at 12.5V, G is

at V

and E is pulsed to V

. The data to be pro-

grammed is applied to 16 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V

is specified to be

6.25V ± 0.25V.

M27C400

6/14

Table 8A. Read Mode AC Characteristics

(1)

= 0 to 70 °C or 40 to 85 °C; V

= 5V ± 5% or 5V ± 10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.
3. Speed obtained with High Speed measurement conditions.

Table 8B. Read Mode AC Characteristics

(1)

= 0 to 70 °C or 40 to 85 °C; V

= 5V ± 5% or 5V ± 10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

M27C400

Unit

-55

(3)

-70

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

, G = V

BHQV

BYTE High to Output Valid

E = V

, G = V

ELQV

Chip Enable Low to Output Valid

G = V

GLQV

Output Enable Low to Output Valid

E = V

BLQZ

(2)

STD

BYTE Low to Output Hi-Z

E = V

, G = V

EHQZ

(2)

Chip Enable High to Output Hi-Z

G = V

GHQZ

(2)

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output Transition

E = V

, G = V

BLQX

BYTE Low to Output Transition

E = V

, G = V

Symbol

Alt

Parameter

Test Condition

M27C400

Unit

-80

-100

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

, G = V

100

BHQV

BYTE High to Output Valid

E = V

, G = V

100

ELQV

Chip Enable Low to Output Valid

G = V

100

GLQV

Output Enable Low to Output Valid

E = V

BLQZ

(2)

STD

BYTE Low to Output Hi-Z

E = V

, G = V

EHQZ

(2)

Chip Enable High to Output Hi-Z

G = V

GHQZ

(2)

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output Transition

E = V

, G = V

BLQX

BYTE Low to Output Transition

E = V

, G = V

M27C400

8/14

Figure 7. BYTE Transition AC Waveforms

Note: Chip Enable (E) and Output Enable (G) = V

AI01638B

tAXQX

tBHQV

A0-A17

BYTEVPP

tAVQV

tBLQX

tBLQZ

VALID

Hi-Z

DATA OUT

VALID

Q0-Q7

Q8-Q15

Table 9. Programming Mode DC Characteristics

(1)

= 25 °C; V

= 6.25V ± 0.25V; V

= 12.5V ± 0.25V)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

±1

Supply Current

Program Current

E = V

Input Low Voltage

0.3

0.8

Input High Voltage

2.4

+ 0.5

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 2.5mA

3.5

A9 Voltage

11.5

12.5

9/14

M27C400

Table 10. Programming Mode AC Characteristics

(1)

= 25 °C; V

= 6.25V ± 0.25V; V

= 12.5V ± 0.25V)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

AVEL

Address Valid to Chip Enable Low

µs

QVEL

Input Valid to Chip Enable Low

µs

VPHAV

VPS

High to Address Valid

µs

VCHAV

VCS

High to Address Valid

µs

ELEH

Chip Enable Program Pulse Width

µs

EHQX

Chip Enable High to Input Transition

µs

QXGL

OES

Input Transition to Output Enable Low

µs

GLQV

Output Enable Low to Output Valid

120

GHQZ

(2)

DFP

Output Enable High to Output Hi-Z

130

GHAX

Output Enable High to Address
Transition

Figure 8. Programming and Verify Modes AC Waveforms

tAVEL

VALID

AI01639

A0-A17

Q0-Q15

BYTEVPP

VCC

DATA IN

DATA OUT

tQVEL

tVPHAV

tVCHAV

tEHQX

tELEH

tGLQV

tQXGL

tGHQZ

tGHAX

PROGRAM

VERIFY

M27C400

10/14

Figure 9. Programming Flowchart

AI01044B

n = 0

Last

Addr

VERIFY

E = 50

s Pulse

++n

= 25

++ Addr

VCC = 6.25V, VPP = 12.5V

FAIL

CHECK ALL WORDS

BYTEVPP =VIH

1st: VCC = 6V

2nd: VCC = 4.2V

YES

PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 26 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
gin. No overpromise pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
Program Inhibit
Programming of multiple M27C400s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C400 may be common. A TTL low level pulse
applied to a M27C400's E input and V

at 12.5V,

will program that M27C400. A high level E input in-
hibits the other M27C400s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at V

and G at V

, V

at 12.5V and V

6.25V.

On-Board Programming
The M27C400 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C400. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C400, with V

= V

= 5V. Two identifier

bytes may then be sequenced from the device out-
puts by toggling address line A0 from V

to V

. All

other address lines must be held at V

during

Electronic Signature mode.
Byte 0 (A0 = V

) represents the manufacturer

code and byte 1 (A0 = V

) the device identifier

code. For the STMicroelectronics M27C400, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q7 to Q0.

ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27C400 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C400 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C400 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27C400 window to prevent unintentional era-
sure. The recommended erasure procedure for
M27C400 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The inte-
grated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 30 W-sec/cm

The erasure time with this dosage is approximate-
ly 30 to 40 minutes using an ultraviolet lamp with
12000 µW/cm

power rating. The M27C400

should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.

M27C400

12/14

Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

5.72

0.225

0.51

1.40

0.020

0.055

3.91

4.57

0.154

0.180

3.89

4.50

0.153

0.177

0.41

0.56

0.016

0.022

1.45

0.057

0.23

0.30

0.009

0.012

51.79

52.60

2.039

2.071

48.26

1.900

15.24

0.600

13.06

13.36

0.514

0.526

2.54

0.100

ea.

14.99

0.590

16.18

18.03

0.637

0.710

3.18

0.125

1.52

2.49

0.060

0.098

8.13

0.320

4°

11°

4°

11°

Figure 10. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline

Drawing is not to scale.

FDIPW-a

13/14

M27C400

Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

4.45

0.175

0.64

0.38

0.025

0.015

3.56

3.91

0.140

0.154

0.38

0.53

0.015

0.021

1.14

1.78

0.045

0.070

0.20

0.31

0.008

0.012

51.78

52.58

2.039

2.070

48.26

1.900

14.80

16.26

0.583

0.640

13.46

13.99

0.530

0.551

2.54

0.100

ea.

15.24

0.600

15.24

17.78

0.600

0.700

3.05

3.81

0.120

0.150

1.52

2.29

0.060

0.090

0°

15°

0°

15°

Figure 11. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline

Drawing is not to scale.

PDIP

M27C400

14/14

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners.

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