1/14
October 2002
M27C64A
64 Kbit (8Kb x8) UV EPROM and OTP EPROM
s
5V 10% SUPPLY VOLTAGE in READ
OPERATION
s
ACCESS TIME: 100ns
s
LOW POWER "CMOS" CONSUMPTION:
Active Current 30mA
Standby Current 100A
s
PROGRAMMING VOLTAGE: 12.5V 0.25V
s
HIGH SPEED PROGRAMMING
(less than 1 minute)
s
ELECTRONIC SIGNATURE
Manufacturer Code: 9Bh
Device Code: 08h
DESCRIPTION
The M27C64A is a 64Kbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and
is organized as 8,192 by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only on time and erasure is not required, the
M27C64A is offered in PLCC32 package.
1
28
FDIP28W (F)
PLCC32 (K)
Figure 1. Logic Diagram
AI00834B
13
A0-A12
P
Q0-Q7
VPP
VCC
M27C64A
G
E
VSS
8
M27C64A
2/14
Figure 2B. Pin Connections
AI00836
NC
A8
A10
Q4
17
A0
NC
Q0
Q1
Q2
DU
Q3
A6
A3
A2
A1
A5
A4
9
P
A9
1
V
PP
A11
Q6
A7
Q7
32
DU
V
CC
M27C64A
A12
NC
Q5
G
E
25
V
SS
Figure 2A. DIP Connections
Q2
VSS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
E
Q3
A11
Q7
Q6
Q4
NC
P
A12
A4
VPP
VCC
A7
AI00835
M27C64A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
20
19
18
17
16
15
A6
A5
A9
A8
28
27
26
25
24
23
22
21
Table 1. Signal Names
A0-A12
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
DU
Don't Use
DEVICE OPERATION
The modes of operation of the M27C64A are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27C64A has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
3/14
M27C64A
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V 0.5V.
Table 4. Electronic Signature
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
G
P
A9
V
PP
Q70-Q0
Read
V
IL
V
IL
V
IH
X
V
CC
Data Out
Output Disable
V
IL
V
IH
V
IH
X
V
CC
Hi-Z
Program
V
IL
X
V
IL
Pulse
X
V
PP
Data Input
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Output
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
1
0
0
1
1
0
1
1
9Bh
Device Code
V
IH
0
0
0
0
1
0
0
0
08h
M27C64A
4/14
Standby Mode
The M27C64A has a standby mode which reduces
the active current from 30mA to 100A. The
M27C64A is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Table 5. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.4V to 2.4V
Input and Output Timing Ref. Voltages
0.8 to 2.0V
Figure 3. AC Testing Input Output Waveform
AI00826
2.4V
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI00828
1.3V
OUT
CL = 100pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25 C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
5/14
M27C64A
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C: V
CC
= 5V 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
30
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V
100
A
I
PP
Program Current
V
PP
= V
CC
100
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400A
2.4
V
Output High Voltage CMOS
I
OH
= 100A
V
CC
0.7V
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1F ceram-
ic capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
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