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March 2000

M27V160

16 Mbit (2Mb x8 or 1Mb x16)

Low Voltage UV EPROM and OTP EPROM

3V to 3.6V LOW VOLTAGE in READ
OPERATION

ACCESS TIME: 100ns

BYTE-WIDE or WORD-WIDE
CONFIGURABLE

16 Mbit MASK ROM REPLACEMENT

LOW POWER CONSUMPTION

Active Current 30mA at 8MHz

Standby Current 60

PROGRAMMING VOLTAGE: 12.5V

0.25V

PROGRAMMING TIME: 50

s/word

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: B1h

DESCRIPTION
The M27V160 is a low voltage 16 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage. It is organised as either 2 Mbit
words of 8 bit or 1 Mbit words of 16 bit. The pin-out
is compatible with a 16 Mbit Mask ROM.
The M27V160 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V160 is offered in PDIP42 and SO44 packag-
es.

FDIP42W (F)

SO44 (M)

PDIP42 (B)

Figure 1. Logic Diagram

AI01898

A0-A19

BYTEVPP

Q0-Q14

VCC

M27V160

VSS

Q15A1

M27V160

2/15

Figure 2B. SO Connections

VSS

A13

VSS

A14

A15

A12

A16

BYTEVPP

Q15A-1

VCC

Q11

Q14

A19

A18

AI01900

M27V160

Q13

A11

A10

Q10

Q12

A17

Figure 2A. DIP Connections

VSS

A13

VSS

A14

A15

A12

A16

BYTEVPP

Q15A-1

VCC

Q11

Q14

A17

A18

A19

AI01899

M27V160

Q13

A11

A10

Q10

Q12

Table 1. Signal Names

A0-A19

Address Inputs

Q0-Q7

Data Outputs

Q8-Q14

Data Outputs

Q15A1

Data Output / Address Input

Chip Enable

Output Enable

BYTEV

Byte Mode / Program Supply

Supply Voltage

Ground

Not Connected Internally

DEVICE OPERATION
The operating modes of the M27V160 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V

and 12V on A9 for the

Electronic Signature.
Read Mode
The M27V160 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV

pin. When BYTEV

is at V

the Word-wide organisation is selected

and the Q15A1 pin is used for Q15 Data Output.
When the BYTEV

pin is at V

the Byte-wide or-

ganisation is selected and the Q15A1 pin is used
for the Address Input A1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A1 at V

the

lower 8 bits of the 16 bit data are selected and with
A1 at V

the upper 8 bits of the 16 bit data are

selected.

3/15

M27V160

The M27V160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to

the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t

AVQV

) is equal to the delay

from E to output (t

ELQV

). Data is available at the

output after a delay of t

GLQV

from the falling edge

of G, assuming that E has been low and the ad-
dresses have been stable for at least t

AVQV

-t

GLQV

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = V

or V

, V

= 12V

0.5V.

Table 4. Electronic Signature

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 125

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

(2)

A9 Voltage

2 to 13.5

Program Supply Voltage

2 to 14

Mode

BYTEV

Q15A1

Q14-Q8

Q7-Q0

Read Word-wide

Data Out

Read Byte-wide Upper

Hi-Z

Data Out

Read Byte-wide Lower

Hi-Z

Data Out

Output Disable

Hi-Z

Program

Pulse

Data In

Verify

Data Out

Program Inhibit

Hi-Z

Standby

Hi-Z

Electronic Signature

Code

Codes

Identifier

Q15

and

Q14

and

Q13

and

Q12

and

Q11

and

Q10

and

Hex Data

Manufacturer's Code

20h

Device Code

B1h

M27V160

4/15

Standby Mode
The M27V160 has a standby mode which reduces
the active current from 20mA to 20

A with low volt-

age operation V

3.6V, see Read Mode DC

Characteristics table for details.The M27V160 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

Table 5. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

3.3k

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance

(1)

= 25

C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance (except BYTEV

)

= 0V

Input Capacitance (BYTEV

)

= 0V

120

OUT

Output Capacitance

OUT

= 0V

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M27V160

Table 7. Read Mode DC Characteristics

(1)

= 0 to 70

C or 40 to 85

C; V

= 3.3V

10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

OUT

Supply Current

E = V

, G = V

, I

OUT

= 0mA,

f = 8MHz, V

3.6V

E = V

, G = V

, I

OUT

= 0mA,

f = 5MHz, V

3.6V

CC1

Supply Current (Standby) TTL

E = V

CC2

Supply Current (Standby) CMOS

E > V

0.2V, V

3.6V

Program Current

= V

Input Low Voltage

0.3

0.2V

(2)

Input High Voltage

0.7V

+ 1

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400

2.4

System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I

has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-

put control and by properly selected decoupling
capacitors. It is recommended that a 0.1

F ceram-

ic capacitor is used on every device between V

and V

. This should be a high frequency type of

low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7

F electrolytic capacitor should be used be-

tween V

and V

for every eight devices. This

capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.

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