1/15

May 1998

M27V256

256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM

LOW VOLTAGE READ OPERATION:
3V to 3.6V

FAST ACCESS TIME: 90ns

LOW POWER CONSUMPTION:

Active Current 10mA at 5MHz

Standby Current 10

PROGRAMMING VOLTAGE: 12.75V

0.25V

PROGRAMMING TIME: 100

s/byte (typical)

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: 8Dh

DESCRIPTION
The M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is orga-
nized as 32,768 by 8 bits.
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.

Figure 1. Logic Diagram

AI01908

A0-A14

Q0-Q7

VPP

VCC

M27V256

VSS

Table 1. Signal Names

A0-A14

Address Inputs

Q0-Q7

Data Outputs

Chip Enable

Output Enable

Program Supply

Supply Voltage

Ground

FDIP28W (F)

PDIP28 (B)

PLCC32 (K)

TSOP28 (N)

8 x 13.4mm

M27V256

2/15

Figure 2B. LCC Pin Connections

Warning: NC = Not Connected, DU = Dont't Use.

AI01910

A13

A10

A14

A11

M27V256

A12

Figure 2A. DIP Pin Connections

A13

A10

A14

A11

VSS

A12

VPP

VCC

AI01909

M27V256

For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.

DEVICE OPERATION
The modes of operation of the M27V256 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
els except for V

and 12V on A9 for Electronic

Signature.
Read Mode
The M27V256 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t

AVQV

) is equal to the delay from E to output

ELQV

). Data is available at the output after delay

of t

GLQV

from the falling edge of G, assuming that

E has been low and the addresses have been sta-
ble for at least t

AVQV

-t

GLQV

Figure 2C. TSOP Pin Connections

A11

A13

A14

A12

VPP

VCC

AI01911

M27V256

VSS

A10

3/15

M27V256

Standby Mode
The M27V256 has a standby mode which reduces
the supply current from 10mA to 10

A with low

voltage operation V

3.6V, see Read Mode DC

Characteristics table for details. The M27V256 is

placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = V

or V

, V

= 12V

0.5V.

Table 4. Electronic Signature

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 125

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

(2)

A9 Voltage

2 to 13.5

Program Supply Voltage

2 to 14

Mode

Q0-Q7

Read

Data Out

Output Disable

Hi-Z

Program

Pulse

Data In

Verify

Data Out

Program Inhibit

Hi-Z

Standby

Hi-Z

Electronic Signature

Codes

Identifier

Hex Data

Manufacturer's Code

20h

Device Code

8Dh

M27V256

4/15

Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the

system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I

, has three seg-

ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.

Table 5. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

3.3k

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance

(1)

= 25

C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Symbol

Parameter

Test Condit ion

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

5/15

M27V256

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70

C or 40 to 85

C; V

= 3.3V

10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Table 8A. Read Mode AC Characteristics

(1)

= 0 to 70

C or 40 to 85

; V

= 3.3V

10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

OUT

Supply Current

E = V

, G = V

, I

OUT

= 0mA,

f = 5MHz, V

3.6V

CC1

Supply Current (Standby) TTL

E = V

CC2

Supply Current (Standby) CMOS

E > V

0.2V, V

3.6V

Program Current

= V

Input Low Voltage

0.3

0.8

(2)

Input High Voltage

+ 1

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400

2.4

Output High Voltage CMOS

= 100

Vcc 0.7V

Symbol

Alt

Parameter

Test Condition

M27V256

Unit

-90

(3)

-100

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

, G = V

100

ELQV

Chip Enable Low to Output Valid

G = V

100

GLQV

Output Enable Low to Output Valid

E = V

EHQZ

(2)

Chip Enable High to Output Hi-Z

G = V

GHQZ

(2)

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output
Transition

E = V

, G = V

The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1

F ceramic

capacitor be used on every device between V

and V

. This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-
tion, a 4.7

F bulk electrolytic capacitor should be

used between V

and V

for every eight devic-

es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

M27V256

6/15

Figure 5. Read Mode AC Waveforms

AI00758B

tAXQX

tEHQZ

A0-A14

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

Table 8B. Read Mode AC Characteristics

(1)

= 0 to 70

C or 40 to 85

C; V

= 3.3V

10%; V

= Vcc)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

M27V256

Unit

-120

-150

-200

Min

Max

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

, G = V

120

150

200

ELQV

Chip Enable Low to Output
Valid

G = V

120

150

200

GLQV

Output Enable Low to Output
Valid

E = V

EHQZ

(2)

Chip Enable High to Output
Hi-Z

G = V

GHQZ

(2)

Output Enable High to Output
Hi-Z

E = V

AXQX

Address Transition to Output
Transition

E = VIL, G = VIL

Programming
The M27V256 has been designed to be fully com-
patible with the M27C256B and has the same
electronic signature. As a result the M27V256 can
be programmed as the M27C256B on the same
programming equipments applying 12.75V on V

and 6.25V on V

by the use of the same PRES-

TO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V256
are in the '1' state. Data is introduced by selective-
ly programming '0's into the desired bit locations.

Although only '0's will be programmed, both '1's
and '0's can be present in the data word. The only
way to change a '0' to a '1' is by die exposition to
ultraviolet light (UV EPROM). The M27V256 is in
the programming mode when V

input is at

12.75V, G is at V

and E is pulsed to V

. The data

to be programmed is applied to 8 bits in parallel to
the data output pins. The levels required for the
address and data inputs are TTL. V

is specified

to be 6.25 V

0.25 V.

7/15

M27V256

Table 9. Programming Mode AC Characteristics

(1)

= 25

C; V

= 6.25V

0.25V; V

= 12.75V

0.25V)

Note: V

must be applied simultaneously with or before V

and removed simultaneously or after V

Table 10. Programming Mode AC Characteristics

(1)

= 25

C; V

= 6.25V

0.25V; V

= 12.75V

0.25V

Note: V

must be applied simultaneously with or before V

and removed simultaneously or after V

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Supply Current

Program Current

E = V

Input Low Voltage

0.3

0.8

Input High Voltage

+ 0.5

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 1mA

3.6

A9 Voltage

11.5

12.5

Symbol

Alt

Parameter

Test Condi tion

Min

Max

Unit

AVEL

Address Valid to Chip Enable Low

QVEL

Input Valid to Chip Enable Low

VPHEL

VPS

High to Chip Enable Low

VCHEL

VCS

High to Chip Enable Low

ELEH

Chip Enable Program Pulse Width

105

EHQX

Chip Enable High to Input Transition

QXGL

OES

Input Transition to Output Enable Low

GLQV

Output Enable Low to Output Valid

100

GHQZ

DFP

Output Enable High to Output Hi-Z

130

GHAX

Output Enable High to Address
Transition

M27V256

8/15

PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100

s program pulses to each byte until a cor-

rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at V

much higher than

3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27V256s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V256 may be common. A TTL low level pulse
applied to a M27V256's E input, with V

at 12.75

V, will program that M27V256. A high level E input
inhibits the other M27V256s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V

, E at V

, V

at 12.75V and V

at 6.25V.

Figure 6. rogramming and Verify Modes AC Waveforms

tAVEL

VALID

AI00759

A0-A14

Q0-Q7

VPP

VCC

DATA IN

DATA OUT

tQVEL

tVPHEL

tVCHEL

tEHQX

tELEH

tGLQV

tQXGL

tGHQZ

tGHAX

PROGRAM

VERIFY

Figure 7. Programming Flowchart

AI00760B

n = 0

Last

Addr

VERIFY

E = 100

s Pulse

++n

= 25

++ Addr

VCC = 6.25V, VPP = 12.75V

FAIL

CHECK ALL BYTES

1st: VCC = 6V

2nd: VCC = 4.2V

YES

9/15

M27V256

On-Board Programming
The M27V256 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25

C am-

bient temperature range that is required when pro-
gramming the M27V256. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V256, with
V

= V

= 5V. Two identifier bytes may then be

sequenced from the device outputs by toggling ad-
dress line A0 from V

to V

. All other address

lines must be held at V

during Electronic Signa-

ture mode. Byte 0 (A0=V

) represents the manu-

facturer code and byte 1 (A0=V

) the device

identifier

code.

For

the

STMicroelectronics

M27V256, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
Note that the M27V256 and M27C256B have the
same identifier bytes.

ERASURE OPERATION (applies for UV EPROM)
The erasure characteristics of the M27V256 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27V256 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V256 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V256 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27V256 is exposure to short wave ultraviolet
light which has wavelength 2537Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm

. The era-

sure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000

W/cm

power rating. The M27V256 should be

placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before era-
sure.

M27V256

10/15

Table 11. Ordering Information Scheme

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

Example:

M27V256

-90

Device Type

Speed

-90

(1)

= 90 ns

-100 = 100 ns

-120 = 120 ns
-150 = 150 ns

-200 = 200 ns

Package
F = FDIP28W

B = PDIP28
K = PLCC32

N = TSOP28: 8 x 13.4mm

Temperature Range
1 = 0 to 70

6 = 40 to 85

Optio n
TR =Tape & Reel Packing

11/15

M27V256

Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

5.72

0.225

0.51

1.40

0.020

0.055

3.91

4.57

0.154

0.180

3.89

4.50

0.153

0.177

0.41

0.56

0.016

0.022

1.45

0.057

0.23

0.30

0.009

0.012

36.50

37.34

1.437

1.470

33.02

1.300

15.24

0.600

13.06

13.36

0.514

0.526

2.54

0.100

14.99

0.590

16.18

18.03

0.637

0.710

3.18

0.125

1.52

2.49

0.060

0.098

7.11

0.280

Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

Drawing is not to scale.

FDIPW-a

M27V256

12/15

Table 13. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

5.08

0.200

0.38

0.015

3.56

4.06

0.140

0.160

0.38

0.51

0.015

0.020

1.52

0.060

0.20

0.30

0.008

0.012

36.83

37.34

1.450

1.470

33.02

1.300

15.24

0.600

13.59

13.84

0.535

0.545

2.54

0.100

14.99

0.590

15.24

17.78

0.600

0.700

3.18

3.43

0.125

0.135

1.78

2.08

0.070

0.082

Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

Drawing is not to scale.

PDIP

13/15

M27V256

Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

2.54

3.56

0.100

0.140

1.52

2.41

0.060

0.095

0.38

0.015

0.33

0.53

0.013

0.021

0.66

0.81

0.026

0.032

12.32

12.57

0.485

0.495

11.35

11.56

0.447

0.455

9.91

10.92

0.390

0.430

14.86

15.11

0.585

0.595

13.89

14.10

0.547

0.555

12.45

13.46

0.490

0.530

1.27

0.050

0.00

0.25

0.000

0.010

0.89

0.035

0.10

0.004

Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

Drawing is not to scale.

PLCC

E1 E

1 N

D2/E2

0.51 (.020)

1.14 (.045)

M27V256

14/15

Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline

Drawing is not to scale

TSOP-c

DIE

Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

1.00

1.25

0.039

0.049

0.20

0.008

0.95

1.05

0.037

0.041

0.30

0.012

0.10

0.21

0.004

0.008

13.10

13.70

0.516

0.539

11.70

11.90

0.461

0.469

7.90

8.25

0.311

0.325

0.55

0.022

0.30

0.70

0.012

0.028

0.10

0.004

15/15

M27V256

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://w ww.st.com

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M27V256-150N1TR

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M27V256-150N1TR