1/15

May 1998

M27V402

4 Mbit (256Kb x 16) Low Voltage UV EPROM and OTP EPROM

LOW VOLTAGE READ OPERATION:
3V to 3.6V

FAST ACCESS TIME: 120ns

LOW POWER CONSUMPTION:

Active Current 15mA at 5MHz

Standby Current 20

PROGRAMMING VOLTAGE: 12.75V

0.25V

PROGRAMMING TIME: 100

s/byte (typical)

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: 8Dh

DESCRIPTION
The M27V402 is a low voltage, low power 4 Mbit
UV

erasable

and

electrically

programmable

EPROM, ideally suited for handheld and portable
microprocessor systems requiring large programs.
It is organized as 262,144 by 16 bits.
The M27V402 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.

FDIP40W (F)

PDIP40 (B)

PLCC44 (K)

TSOP40 (N)

10 x 20 mm

Figure 1. Logic Diagram

AI01819

A0-A17

Q0-Q15

VPP

VCC

M27V402

VSS

Table 1. Signal Names

A0-A17

Address Inputs

Q0-Q15

Data Outputs

Chip Enable

Output Enable

Program Supply

Supply Voltage

Ground

M27V402

2/15

Figure 2B. LCC Pin Connections

Warning: NC = Not Connected.

AI01820

A14

A11

Q12

VSS

Q11

Q10

A15

Q15

VSS

A12

Q13

A16

M27V402

Q14

A13

A10

A17

Figure 2A. DIP Pin Connections

Q11

VSS

Q10

A12

A11

A10

A13

VSS

A16

A17

Q12

VPP

VCC

Q15

AI01862

M27V402

Q14

Q13

A14

A15

For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.

DEVICE OPERATION
The operating modes of the M27V402 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V

and 12V on A9 for Electronic

Signature.
Read Mode
The M27V402 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins,
independent of device selection. Assuming that
the addresses are stable, the address access time
(t

AVQV

) is equal to the delay from E to output

ELQV

). Data is available at the output after a delay

of t

GLQV

from the falling edge of G, assuming that

E has been low and the addresses have been
stable for at least t

AVQV

-t

GLQV

Figure 2C. TSOP Pin Connections

DQ6

DQ3

DQ2

DQ13

DQ8

DQ7

DQ10

DQ9

A14

A11

A10

A15

DQ1

DQ0

A16

A17

DQ14

VPP

VCC

DQ15

AI01821

M27V402

(Normal)

VSS

A13

A12

DQ11

DQ12

DQ5

DQ4

VSS

3/15

M27V402

Standby Mode
The M27V402 has a standby mode which reduces
the supply current from 20mA to 20

A with low

voltage operation V

3.6V, see Read Mode DC

Characteristics table for details. The M27V402 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = V

or V

, V

= 12V

0.5V.

Table 4. Electronic Signature

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 125

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

(2)

A9 Voltage

2 to 13.5

Program Supply Voltage

2 to 14

Mode

Q0-Q15

Read

or V

Data Out

Output Disable

or V

Hi-Z

Program

Pulse

Data In

Verify

Data Out

Program Inhibit

Hi-Z

Standby

or V

Hi-Z

Electronic Signature

Codes

Identifier

Hex Data

Manufacturer's Code

20h

Device Code

8Dh

M27V402

4/15

Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

Table 5. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

3.3k

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance

(1)

= 25

C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Symbol

Parameter

Test Condit ion

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

5/15

M27V402

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70

C, 20 to 70

C, 20 to 85

C or 40 to 85

C; V

= 3.3V

10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

OUT

Supply Current

E = V

, G = V

, I

OUT

= 0mA,

f = 5MHz, V

= 3.6V

CC1

Supply Current (Standby) TTL

E = V

CC2

Supply Current (Standby) CMOS

E > V

0.2V, V

= 3.6V

Program Current

= V

Input Low Voltage

0.3

0.8

(2)

Input High Voltage

+ 1

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400

2.4

Output High Voltage CMOS

= 100

0.7V

System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I

, has three seg-

ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the de-
vice.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1

F ceramic

capacitor be used on every device between V

and V

. This should be a high frequency capaci-

tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7

F bulk electrolytic capacitor should be

used between V

and V

for every eight devic-

es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27V402 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposure to ultraviolet
light (UV EPROM). The M27V402 is in the pro-
gramming mode when V

input is at 12.75V, G ia

at V

and E is pulsed to V

. The data to be pro-

grammed is applied to 16 bits in parallel to the data
output pins.
The levels required for the address and data in-
puts are TTL. V

is specified to be 6.25V

0.25V.

M27V402

6/15

Figure 5. Read Mode AC Waveforms

AI00731

tAXQX

tEHQZ

DATA OUT

A0-A17

Q0-Q15

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

Table 8. Read Mode AC Characteristics

(1)

(TA = 0 to 70

C, 20 to 70

C, 20 to 85

C or 40 to 85

C; V

= 3.3V

10%; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

M27V402

Unit

-120

-150

-200

Min

Max

Min

Max

Min

Max

AVQV

ACC

Address Valid to
Output Valid

E = V

, G = V

120

150

200

ELQV

Chip Enable Low to
Output Valid

G = V

120

150

200

GLQV

Output Enable Low to
Output Valid

E = V

100

EHQZ

(2)

Chip Enable High to
Output Hi-Z

G = V

GHQZ

(2)

Output Enable High to
Output Hi-Z

E = V

AXQX

Address Transition to
Output Transition

E = V

, G = V

7/15

M27V402

Table 9. Programming Mode DC Characteristics

(1)

= 25

C; V

= 6.25V

0.25V; V

= 12.75V

0.25V)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

Table 10. Programming Mode AC Characteristics

(1)

= 25

C; V

= 6.25V

0.25V; V

= 12.75V

0.25V)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, not 100% tested.

Symbol

Parameter

Test Conditio n

Min

Max

Unit

Input Leakage Current

Supply Current

Program Current

E = V

Input Low Voltage

0.3

0.8

Input High Voltage

+ 0.5

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400

2.4

A9 Voltage

11.5

12.5

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

AVEL

Address Valid to Chip Enable Low

QVEL

Input Valid to Chip Enable Low

VPHEL

VPS

High to Chip Enable Low

VCHEL

VCS

High to Chip Enable Low

ELEH

Chip Enable Program Pulse Width

105

EHQX

Chip Enable High to Input Transition

QXGL

OES

Input Transition to Output Enable Low

GLQV

Output Enable Low to Output Valid

100

GHQZ

DFP

Output Enable High to Output Hi-Z

130

GHAX

Output Enable High to Address
Transition

M27V402

8/15

PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100

s program pulses to each byte

until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at V

much

higher than 3.6V provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27V402s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V402 may be common. A TTL low level pulse
applied to a M27V402's E input, with V

12.75V, will program that M27V402. A high level E
input inhibits the other M27V402s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V

, E at V

, V

at 12.75V and V

at 6.25V.

Figure 6. Programming and Verify Modes AC Waveforms

tAVEL

VALID

AI00730

A0-A17

Q0-Q15

VPP

VCC

DATA IN

DATA OUT

tQVEL

tVPHEL

tVCHEL

tEHQX

tELEH

tGLQV

tQXGL

tGHQZ

tGHAX

PROGRAM

VERIFY

Figure 7. Programming Flowchart

AI00726C

n = 0

Last

Addr

VERIFY

E = 100

s Pulse

++n

= 25

++ Addr

VCC = 6.25V, VPP = 12.75V

FAIL

CHECK ALL WORDS

1st: VCC = 6V

2nd: VCC = 4.2V

YES

9/15

M27V402

On-Board Programming
The M27V402 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25

C am-

bient temperature range that is required when pro-
gramming the M27V402. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V402 with
V

=5V. Two identifier bytes may then be

sequenced from the device outputs by toggling ad-
dress line A0 from V

to V

. All other address

lines must be held at V

during Electronic Signa-

ture mode. Byte 0 (A0=V

) represents the manu-

facturer code and byte 1 (A0=V

) the device

identifier

code.

For

the

STMicroelectronics

M27V402, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.

ERASURE OPERATION (

applies to

UV EPROM)

The erasure characteristics of the M27V402 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000Å. It should be noted that sunlight
and some type of fluorescent lamps have wave-
lengths in the 3000-4000Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27V402 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V402 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V402 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27V402 is exposure to short wave ultraviolet
light which has a wavelength of 2537Å. The inte-
grated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 15 W-sec/cm

The erasure time with this dosage is approximate-
ly 15 to 20 minutes using an ultraviolet lamp with
12000

W/cm

power rating. The M27V402

should be placed within 2.5 cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.

11/15

M27V402

Table 12. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

5.72

0.225

0.51

1.40

0.020

0.055

3.91

4.57

0.154

0.180

3.89

4.50

0.153

0.177

0.41

0.56

0.016

0.022

1.45

0.057

0.23

0.30

0.009

0.012

51.79

52.60

2.039

2.071

48.26

1.900

15.24

0.600

13.06

13.36

0.514

0.526

2.54

0.100

14.99

0.590

16.18

18.03

0.637

0.710

3.18

0.125

1.52

2.49

0.060

0.098

7.62

0.300

Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Outline

Drawing is not to scale.

FDIPW-a

M27V402

12/15

Table 13. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

4.45

0.175

0.64

0.38

0.025

0.015

3.56

3.91

0.140

0.154

0.38

0.53

0.015

0.021

1.14

1.78

0.045

0.070

0.20

0.31

0.008

0.012

51.78

52.58

2.039

2.070

48.26

1.900

14.80

16.26

0.583

0.640

13.46

13.99

0.530

0.551

2.54

0.100

15.24

0.600

15.24

17.78

0.600

0.700

3.05

3.81

0.120

0.150

1.52

2.29

0.060

0.090

Figure 9. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Outline

Drawing is not to scale.

PDIP

13/15

M27V402

Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, square, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

4.20

4.70

0.165

0.185

2.29

3.04

0.090

0.120

0.51

0.020

0.33

0.53

0.013

0.021

0.66

0.81

0.026

0.032

17.40

17.65

0.685

0.695

16.51

16.66

0.650

0.656

14.99

16.00

0.590

0.630

17.40

17.65

0.685

0.695

16.51

16.66

0.650

0.656

14.99

16.00

0.590

0.630

1.27

0.050

0.00

0.25

0.000

0.010

0.89

0.035

0.10

0.004

Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, square, Package Outline

Drawing is not to scale.

PLCC

E1 E

1 N

D2/E2

0.51 (.020)

1.14 (.045)

M27V402

14/15

Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

Drawing is not to scale

TSOP-a

N/2

DIE

Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symb

inches

Typ

Min

Max

Typ

Min

Max

1.20

0.047

0.05

0.15

0.002

0.006

0.95

1.05

0.037

0.041

0.17

0.27

0.007

0.011

0.10

0.21

0.004

0.008

19.80

20.20

0.780

0.795

18.30

18.50

0.720

0.728

9.90

10.10

0.390

0.398

0.50

0.020

0.50

0.70

0.020

0.028

0.10

0.004

15/15

M27V402

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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