1/16
May 1998
M27V801
8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM
s
LOW VOLTAGE READ OPERATION:
3V to 3.6V
s
FAST ACCESS TIME: 120ns
s
LOW POWER CONSUMPTION:
Active Current 15mA at 5MHz
Standby Current 20
A
s
PROGRAMMING VOLTAGE: 12.75V
0.25V
s
PROGRAMMING TIME: 100
s/byte (typical)
s
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code: 42h
DESCRIPTION
The M27V801 is a low voltage 8 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 1,048,576 by
8 bits.
The M27V801 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP32W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
Figure 1. Logic Diagram
AI01902
20
A0-A19
Q0-Q7
VCC
M27V801
VSS
8
GVPP
E
Table 1. Signal Names
A0-A19
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
GV
PP
Output Enable / Program Supply
V
CC
Supply Voltage
V
SS
Ground
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
32
1
FDIP32W (F)
PDIP32 (B)
1
32
M27V801
2/16
Figure 2B. PLCC Pin Connections
AI01904
A17
A8
A10
Q5
17
A1
A0
Q0
Q1
Q2
Q3
Q4
A7
A4
A3
A2
A6
A5
9
A18
A9
1
A16
A11
A13
A12
Q7
32
A19
V
CC
M27V801
A15
A14
Q6
GVPP
E
25
V
SS
Figure 2A. DIP Pin Connections
A1
A0
Q0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11
GVPP
E
Q5
Q1
Q2
Q3
VSS
Q4
Q6
A17
A18
A16
A12
A19
VCC
A15
AI01903
M27V801
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2C. TSOP Pin Connections
A1
A0
Q0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
Q7
A14
A11
GVPP
E
Q5
Q1
Q2
Q3
Q4
Q6
A17
A18
A16
A12
A19
VCC
A15
AI01905
M27V801
(Normal)
8
1
9
16
17
24
25
32
VSS
For applications where the content is programmed
only one time and erasure is not required, the
M27V801 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V801 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for GV
PP
and 12V on A9 for Elec-
tronic Signature and Margin Mode Set or Reset .
Read Mode
The M27V801 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
3/16
M27V801
Standby Mode
The M27V801 has a standby mode which reduces
the active current from 15mA to 20
A with low volt-
age operation V
CC
3.6V, see Read Mode DC
Characteristics table for details.The M27V801 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the GV
PP
input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V
0.5V.
Table 4. Electronic Signature
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
GV
PP
A9
Q0-Q7
Read
V
IL
V
IL
X
Data Out
Output Disable
V
IL
V
IH
X
Hi-Z
Program
V
IL
Pulse
V
PP
X
Data In
Program Inhibit
V
IH
V
PP
X
Hi-Z
Standby
V
IH
X
X
Hi-Z
Electronic Signature
V
IL
V
IL
V
ID
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
1
0
0
0
0
1
0
42h
M27V801
4/16
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7
F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
5/16
M27V801
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 3.3V
10%)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 3.3V
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
2. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V, V
CC
3.6V
20
A
I
PP
Program Current
V
PP
= V
CC
10
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
A
2.4
V
Output High Voltage CMOS
I
OH
= 100
A
V
CC
0.7V
V
Symbol
Alt
Parameter
Test Condi tion
M27V801
Unit
-120
-150
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, GV
PP
= V
IL
120
150
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
GV
PP
= V
IL
120
150
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
60
80
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output Hi-Z
GV
PP
= V
IL
0
50
0
50
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
50
0
50
ns
t
AXQX
t
OH
Address Transition to Output Transition
E = V
IL
, GV
PP
= V
IL
0
0
ns
M27V801
6/16
Figure 5. Read Mode AC Waveforms
AI01583B
tAXQX
tEHQZ
A0-A19
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table 8B. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 3.3V
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
Test Condi tion
M27V801
Unit
-180
-200
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, GV
PP
= V
IL
180
200
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
GV
PP
= V
IL
180
200
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
90
100
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output Hi-Z
GV
PP
= V
IL
0
50
0
70
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
50
0
70
ns
t
AXQX
t
OH
Address Transition to Output Transition
E = V
IL
, GV
PP
= V
IL
0
0
ns
7/16
M27V801
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. MARGIN MODE AC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Symbol
Parameter
Test Conditio n
Min
Max
Unit
I
LI
Input Leakage Current
V
IL
V
IN
V
IH
10
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.4
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 1mA
3.6
V
V
ID
A9 Voltage
11.5
12.5
V
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
A9HVPH
t
AS9
V
A9
High to V
PP
High
2
s
t
VPHEL
t
VPS
V
PP
High to Chip Enable Low
2
s
t
A10HEH
t
AS10
V
A10
High to Chip Enable High (Set)
1
s
t
A10LEH
t
AS10
V
A10
Low to Chip Enable High (Reset)
1
s
t
EXA10X
t
AH10
Chip Enable Transition to V
A10
Transition
1
s
t
EXVPX
t
VPH
Chip Enable Transition to V
PP
Transition
2
s
t
VPXA9X
t
AH9
V
PP
Transition to V
A9
Transition
2
s
Programming
The M27V801 has been designed to be fully com-
patible with the M27C801 and has the same elec-
tronic signature. As a result the M27V801 can be
programmed as the M27C801 on the same pro-
gramming equipments applying 12.75V on V
PP
and 6.25V on V
CC
by the use of the same PRES-
TO IIB algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V801
are in the '1' state. Data is introduced by selective-
ly programming '0's into the desired bit locations.
Although only '0' will be programmed, both '1' and
'0' can be present in the data word. The only way
to change a '0' to a '1' is by die exposure to ultravi-
olet light (UV EPROM). The M27V801 is in the
programming mode when V
PP
input is at 12.75V
and E is pulsed to V
IL
. The data to be programmed
is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data
inputs are TTL. V
CC
is specified to be 6.25V
0.25V.
The M27V801 can use PRESTO IIB Programming
Algorithm that drastically reduces the program-
ming time (typically 52 seconds). Nevertheless to
achieve compatibility with all programming equip-
ments, PRESTO Programming Algorithm can be
used.
M27V801
8/16
Table 11. Programming Mode AC Characteristics
(1)
(T
A
= 25
C; V
CC
= 6.25V
0.25V; V
PP
= 12.75V
0.25V)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
2
s
t
QVEL
t
DS
Input Valid to Chip Enable Low
2
s
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
2
s
t
VPHEL
t
OES
V
PP
High to Chip Enable Low
2
s
t
VPLVPH
t
PRT
V
PP
Rise Time
50
ns
t
ELEH
t
PW
Chip Enable Program Pulse Width (Initial)
45
55
s
t
EHQX
t
DH
Chip Enable High to Input Transition
2
s
t
EHVPX
t
OEH
Chip Enable High to V
PP
Transition
2
s
t
VPLEL
t
VR
V
PP
Low to Chip Enable Low
2
s
t
ELQV
t
DV
Chip Enable Low to Output Valid
1
s
t
EHQZ
(2)
t
DFP
Chip Enable High to Output Hi-Z
0
130
ns
t
EHAX
t
AH
Chip Enable High to Address Transition
0
ns
Figure 6. MARGIN MODE AC Waveforms
Note: A8 High level = 5V; A9 High level = 12V.
AI00736B
tA9HVPH
tVPXA9X
A8
E
GVPP
A10 Set
VCC
tVPHEL
tA10LEH
tEXVPX
tA10HEH
A9
A10 Reset
tEXA10X
9/16
M27V801
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. This can
be achieved with STMicroelectronics M27V801
due to several design innovations to improve pro-
gramming efficiency and to provide adequate mar-
gin for reliability. Before starting the programming
the internal MARGIN MODE circuit is set in order
to guarantee that each cell is programmed with
enough margin. Then a sequence of 50
s pro-
gram pulses are applied to each byte until a cor-
rect verify occurs. No overprogram pulses are
applied since the verify in MARGIN MODE pro-
vides the necessary margin.
Program Inhibit
Programming of multiple M27V801s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including GV
PP
of the par-
allel M27V801 may be common. A TTL low level
pulse applied to a M27V801's E input, with V
PP
at
12.75V, will program that M27V801. A high level E
input inhibits the other M27V801s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V
IL
. Data should be verified with t
ELQV
after the
falling edge of E.
Figure 7. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI01270
A0-A19
Q0-Q7
VCC
DATA IN
DATA OUT
E
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHVPX
tELQV
tELEH
tEHQZ
tVPLEL
PROGRAM
VERIFY
GVPP
tEHAX
Figure 8. Programming Flowchart
AI01271B
n = 0
Last
Addr
VERIFY
E = 50
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
SET MARGIN MODE
RESET MARGIN MODE
M27V801
10/16
On-Board Programming
The M27V801 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25
C
5
C am-
bient temperature range that is required when pro-
gramming the M27V801. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V801. Two
identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from
V
IL
to V
IH
. All other address lines must be held at
V
IL
during Electronic Signature mode.
Byte 0 (A0=V
IL
) represents the manufacturer code
and byte 1 (A0=V
IH
) the device identifier code. For
the STMicroelectronics M27V801, these two iden-
tifier bytes are given in Table 4 and can be read-
out on outputs Q0 to Q7. Note that the M27V801
and M27C801 have the same identifier bytes.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27V801 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 . It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 range.
Research shows that constant exposure to room
level fluorescent lighting could erase a typical
M27V801 in about 3 years, while it would take ap-
proximately 1 week to cause erasure when ex-
posed to direct sunlight. If the M27V801 is to be
exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labels be put over the M27V801 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27V801 is exposure to
short wave ultraviolet light which has wavelength
2537 . The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 30 W-sec/cm
2
. The erasure time with this dos-
age is approximately 30 to 40 minutes using an ul-
traviolet lamp with 12000
W/cm
2
power rating.
The M27V801 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
11/16
M27V801
Table 12. Ordering Information Scheme
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Example:
M27V801
-100 K
1
TR
Device Type
Operating Voltage
V = 3V
Speed
-120 = 120 ns
-150 = 150 ns
-180 = 180 ns
-200 = 200 ns
Package
F = FDIP32W
P = PDIP32
K = PLCC32
N = TSOP32: 8 x 20mm
Temperature Range
1 = 0 to 70
C
6 = 40 to 85
C
Optio n
TR =Tape & Reel Packing
M27V801
12/16
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
5.72
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
41.73
42.04
1.643
1.655
D2
38.10
1.500
E
15.24
0.600
E1
13.06
13.36
0.514
0.526
e
2.54
0.100
eA
14.99
0.590
eB
16.18
18.03
0.637
0.710
L
3.18
0.125
S
1.52
2.49
0.060
0.098
K
6.60
0.260
K1
10.67
0.420
4
11
4
11
N
32
32
Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline
Drawing is not to scale.
FDIPW-b
A3
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
D2
K
K1
eB
A2
13/16
M27V801
Table 14. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
5.08
0.200
A1
0.38
0.015
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
B1
1.52
0.060
C
0.20
0.30
0.008
0.012
D
41.78
42.04
1.645
1.655
D2
38.10
1.500
E
15.24
0.600
E1
13.59
13.84
0.535
0.545
e1
2.54
0.100
eA
15.24
0.600
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
0
10
0
10
N
32
32
Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
Drawing is not to scale.
PDIP
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
eB
D2
M27V801
14/16
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
2.54
3.56
0.100
0.140
A1
1.52
2.41
0.060
0.095
A2
0.38
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
e
1.27
0.050
F
0.00
0.25
0.000
0.010
R
0.89
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
Drawing is not to scale.
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
15/16
M27V801
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.007
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
5
0
5
N
32
32
CP
0.10
0.004
M27V801
16/16
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