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April 2000

M27W101

1 Mbit (128Kb x8) Low Voltage UV EPROM and OTP EPROM

2.7V to 3.6V LOW VOLTAGE in READ
OPERATION

ACCESS TIME:

70ns at V

= 3.0V to 3.6V

80ns at V

= 2.7V to 3.6V

PIN COMPATIBLE with M27C1001

LOW POWER CONSUMPTION:

Active Current 15mA at 5MHz

Standby Current 15µA

PROGRAMMING TIME 100µs/byte

HIGH RELIABILITY CMOS TECHNOLOGY

2,000V ESD Protection

200mA Latchup Protection Immunity

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: 05h

DESCRIPTION
The M27W101 is a low voltage 1 Mbit EPROM of-
fered in two range UV (ultra violet erase) and OTP
(one time programmable). It is ideally suited for mi-
croprocessor systems requiring large data or pro-
gram storage and is organized as 131,072 by 8
bits.
The M27W101 operates in the read mode with a
supply voltage as low as 2.7V at 40 to 85 °C tem-
perature range.
The decrease in operating power allows either a
reduction of the size of the battery or an increase
in the time between battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27W101 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.

Figure 1. Logic Diagram

AI01587

A0-A16

Q0-Q7

VPP

VCC

M27W101

VSS

FDIP32W (F)

PDIP32 (B)

PLCC32 (K)

TSOP32 (N)

8 x 20 mm

M27W101

2/15

Figure 2B. LCC Connections

AI01588

A10

A16

A11

A13

A12

M27W101

A15

A14

Figure 2A. DIP Connections

A13

A10

A14

A11

VSS

A16

A12

VPP

VCC

A15

AI02674

M27W101

Table 1. Signal Names

A0-A16

Address Inputs

Q0-Q7

Data Outputs

Chip Enable

Output Enable

Program

Program Supply

Supply Voltage

Ground

Not Connected Internally

Figure 2C. TSOP Connections

A13

A10

A14

A11

A16

A12

VPP

VCC

A15

AI01589

M27W101

(Normal)

VSS

3/15

M27W101

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = V

or V

, V

= 12V ± 0.5V.

Table 4. Electronic Signature

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 85

°C

BIAS

Temperature Under Bias

50 to 125

°C

STG

Storage Temperature

65 to 150

°C

(2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

(2)

A9 Voltage

2 to 13.5

Program Supply Voltage

2 to 14

Mode

Q7-Q0

Read

or V

Data Out

Output Disable

or V

Hi-Z

Program

Pulse

Data In

Verify

Data Out

Program Inhibit

Hi-Z

Standby

or V

Hi-Z

Electronic Signature

Codes

Identifier

Hex Data

Manufacturer's Code

20h

Device Code

05h

M27W101

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DEVICE OPERATION
The operating modes of the M27W101 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V

and 12V on A9 for Electronic

Signature.
Read Mode
The M27W101 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time

AVQV

) is equal to the delay from E to output

ELQV

). Data is available at the output after a delay

of t

GLQV

from the falling edge of G, assuming that

E has been low and the addresses have been sta-
ble for at least t

AVQV

-t

GLQV

Standby Mode
The M27W101 has a standby mode which reduc-
es the supply current from 15mA to 15µA with low
voltage operation V

3.6V, see Read Mode DC

Characteristics table for details. The M27W101 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

Table 5. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

3.3k

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance

(1)

= 25 °C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

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M27W101

Table 7. Read Mode DC Characteristics

(1)

= 40 to 85°C; V

= 2.7V to 3.6V; V

= V

)

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

±10

µA

Output Leakage Current

OUT

±10

µA

Supply Current

E = V

, G = V

OUT

= 0mA, f = 5MHz,

3.6V

CC1

Supply Current (Standby) TTL

E = V

CC2

Supply Current (Standby) CMOS

E > V

0.2V,

3.6V

µA

Program Current

= V

µA

Input Low Voltage

0.6

0.2 V

(2)

Input High Voltage

0.7 V

+ 0.5

Output Low Voltage

= 2.1mA

0.4

Output High Voltage TTL

= 400µA

2.4

Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I

, has three seg-

ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V

and V

. This should be a high frequency capaci-

tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V

and V

for every eight devic-

es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

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