1/15
April 2000
M27W102
1 Mbit (64Kb x16) Low Voltage UV EPROM and OTP EPROM
s
2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
s
READ ACCESS TIME:
70ns at V
CC
= 3.0V to 3.6V
80ns at V
CC
= 2.7V to 3.6V
s
PIN COMPATIBLE with M27C1024
s
LOW POWER CONSUMPTION:
15A max Standby Current
15mA max Active Current at 5MHz
s
PROGRAMMING TIME 100s/word
s
HIGH RELIABILITY CMOS TECHNOLOGY
2,000V ESD Protection
200mA Latchup Protection Immunity
s
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Device Code: 008Ch
DESCRIPTION
The M27W102 is a low voltage 1 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 65,536
words by 16 bits.
The M27W102 operates in the read mode with a
supply voltage as low as 2.7V at 40 to 85C tem-
perature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery re-
charges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27w102 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
Figure 1. Logic Diagram
AI01922
16
A0-A15
P
Q0-Q15
VPP
VCC
M27W102
G
E
VSS
16
1
40
1
40
FDIP40W (F)
PDIP40 (B)
PLCC44 (K)
TSOP40 (N)
10 x 14 mm
M27W102
2/15
Figure 2B. LCC Connections
AI01924
A14
A11
A7
A3
23
Q6
Q5
Q4
Q3
Q2
NC
A2
Q12
Q8
VSS
NC
Q11
Q10
12
A15
A9
1
Q15
VSS
A12
Q13
A5
44
NC
NC
M27W102
Q14
A13
A4
NC
A6
34
Q1
Q9
A10
A8
Q7
Q0
G
A0
A1
V
PP
E
P
V
CC
Figure 2A. DIP Connections
Q6
Q5
Q4
Q11
Q8
VSS
Q7
Q10
Q9
A12
A8
A11
A10
A6
A13
A9
VSS
A7
A2
Q1
Q0
A0
G
A1
A5
NC
P
E
Q12
VPP
VCC
Q15
AI02673
M27W102
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q3
Q2
Q14
Q13
A4
A3
40
39
38
37
36
35
34
33
A14
A15
Table 1. Signal Names
A0-A15
Address Inputs
Q0-Q15
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
Figure 2C. TSOP Connections
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A8
A11
A10
A4
A15
A9
G
A7
A2
DQ1
DQ0
A0
A1
A3
NC
P
E
DQ14
VPP
VCC
DQ15
AI01925
M27W102
(Normal)
10
1
11
20
21
30
31
40
VSS
A12
A6
A13
A5
DQ12
DQ4
DQ11
DQ5
VSS
3/15
M27W102
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V 0.5V.
Table 4. Electronic Signature
Note: Outputs Q15-Q8 are set to '0'.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 85
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltage (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Mode
E
G
P
A9
V
PP
Q15-Q0
Read
V
IL
V
IL
V
IH
X
V
CC
or V
SS
Data Out
Output Disable
V
IL
V
IH
X
X
V
CC
or V
SS
Hi-Z
Program
V
IL
X
V
IL
Pulse
X
V
PP
Data Input
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Output
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
or V
SS
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
0
0
1
1
0
0
8Ch
M27W102
4/15
DEVICE OPERATION
The operating modes of the M27W102 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27W102 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
OE
from the falling edge of G, assuming that E
has been low and the addresses have been stable
for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27W102 has a standby mode which reduc-
es the supply current from 15mA to 15A with low
voltage operation V
CC
3.6V, see Read Mode DC
Characteristics table for details. The M27W102 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25 C, f = 1 MHz)
Note: Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
5/15
M27W102
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 40 to 85C; V
CC
= 2.7V to 3.6V; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz,
V
CC
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V,
V
CC
3.6V
15
A
I
PP
Program Current
V
PP
= V
CC
10
A
V
IL
Input Low Voltage
0.6
0.2 V
CC
V
V
IH
(2)
Input High Voltage
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400A
2.4
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1F ceram-
ic capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
PDF 
ZIP