1/23

PRELIMINARY DATA

February 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M28010

1 Mbit (128K x 8) Parallel EEPROM

With Software Data Protection

Fast Access Time: 100 ns

Single Supply Voltage:

4.5 V to 5.5 V for M28010

2.7 V to 3.6 V for M28010-W

1.8 V to 2.4 V for M28010-R

Low Power Consumption

Fast BYTE and PAGE WRITE (up to 128 Bytes)

Enhanced Write Detection and Monitoring:

Data Polling

Toggle Bit

Page Load Timer Status

JEDEC Approved Bytewide Pin-Out

Software Data Protection

Hardware Data Protection

Software Chip Erase

100000 Erase/Write Cycles (minimum)

Data Retention (minimum): 10 Years

DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power,

parallel

EEPROM,

fabricated

with

STMicroelectronics' proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V, 3V or 2V, depending on
the option chosen).

Figure 1. Logic Diagram

AI02221

A0-A16

DQ0-DQ7

VCC

M28010

VSS

Table 1. Signal Names

A0-A16

Address Input

DQ0-DQ7

Data Input / Output

Write Enable

Chip Enable

Output Enable

VCC

Supply Voltage

VSS

Ground

PDIP32 (BA)

PLCC32 (KA)

TSOP32 (NA)

8 x 20 mm

M28010

2/23

Figure 2A. DIP Connections

Note: 1. DU = Do Not Use

Figure 2B. PLCC Connections

Note: 1. DU = Do Not Use

DQ0

A13

A10

DQ7

A14

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A12

VCC

AI02222

M28010

A15

A16

AI02223

A10

DQ4

DQ0

DQ1

DQ2

DQ6

DQ3

A16

A11

A14

A12

DQ7

M28010

A15

A13

DQ5

Figure 2C. TSOP Connections

Note: 1. DU = Do Not Use

A11

DQ7

DQ5

DQ0

DQ1

DQ3

DQ4

DQ6

A13

A15

A14

VCC

A12

AI02224

M28010

VSS

A10

DQ2

A16

The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software hand-shaking, with Data Polling and
Toggle Bit. The device supports a 128 byte Page
Write operation. Software Data Protection (SDP)
is also supported, using the standard JEDEC
algorithm.
The M28010 is designed for applications requiring
as much as 100,000 write cycles and ten years of

data retention. The organization of the data in a 4
byte (32-bit) "word" format leads to significant
savings in power consumption. Once a byte has
been read, subsequent byte read cycles from the
same "word" (with addresses differing only in the
two least significant bits) are fetched from the
previously loaded Read Buffer, not from the
memory array. As a result, the power consumption
for these subsequent read cycles is much lower
than the power consumption for the first cycle. By
careful design of the memory access patterns, a
50% reduction in the power consumption is
possible.

SIGNAL DESCRIPTION
The external connections to the device are
summarized in Table 1, and their use in Table 3.
Addresses (A0-A16). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, and is used to
initiate read operations.

3/23

M28010

Figure 3. Block Diagram

AI02225

ADDRESS

LATCH

A7-A16

(Page Address)

DECODE

CONTROL

LOGIC

1Mbit ARRAY

ADDRESS

LATCH

A0-A6

I/O BUFFERS

VPP GEN

LATCH PAGE

Y DECODE

SENSE PAGE & DATA LATCH

DQ0-DQ7

ECC

(1)

& MULTIPLEXER

VREAD GEN

REFERENCES

PROGRAMMING

STATE

MACHINE

Table 2. Absolute Maximum Ratings

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500

)

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

40 to 85

STG

Storage Temperature

65 to 150

Supply Voltage

0.3 to V

CCMAX

Input or Output Voltage (except A9)

0.3 to V

+0.6

Input Voltage

0.3 to 4.5

ESD

Electrostatic Discharge Voltage (Human Body model)

2000

M28010

4/23

Table 3. Operating Modes

Note: 1. X = V

or V

Mode

DQ0-DQ7

Read

Data Out

Write

Data In

Stand-by / Write Inhibit

Hi-Z

Write Inhibit

Data Out or Hi-Z

Write Inhibit

Data Out or Hi-Z

Output Disable

Hi-Z

Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.

DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V

comparator

inhibits the Write operations if the V

voltage is

lower than V

(see Table 4A to Table 4C). Once

the voltage applied on the V

pin goes over the

threshold (V

), write access to the

memory is allowed after a time-out t

PUW

, as

specified in Table 4A to Table 4C.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.

Table 4A. Power-Up Timing

for M28010 (5V range)

= 40 to 85

C; V

= 4.5 to 5.5 V)

Note: 1. Sampled only, not 100% tested.

Table 4B. Power-Up Timing

for M28010-W (3V range)

= 40 to 85

C; V

= 2.7 to 3.6 V)

Note: 1. Sampled only, not 100% tested.

Table 4C. Power-Up Timing

for M28010-R (2V range)

= 40 to 85

C; V

= 1.8 to 2.4 V)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Min.

Max.

Unit

PUR

Time Delay to Read Operation

PUW

Time Delay to Write Operation (once V

)

Write Inhibit Threshold

3.0

4.2

Symbol

Parameter

Min.

Max.

Unit

PUR

Time Delay to Read Operation

PUW

Time Delay to Write Operation (once V

)

Write Inhibit Threshold

2.0

2.6

Symbol

Parameter

Min.

Max.

Unit

PUR

Time Delay to Read Operation

PUW

Time Delay to Write Operation (once V

)

Write Inhibit Threshold

1.2

1.7

5/23

M28010

Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)

Wait for write completion (tQ5HQ5X)

AI02227B

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

SDP is set

Page Write

Timing

SDP is Disabled and Application

needs to Enable it, and Write Data

Time Out (tWLQ5H)

DATA has been written

and SDP is Enabled

SDP is Disabled and

Application needs to Enable it

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

Page Write

Timing

DATA has been written

and SDP is Enabled

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Write
is enabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

Page Write

Timing

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Write
is enabled

Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as

shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, t

WLQ5H

, that cannot be shorter than

the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle

M28010

6/23

Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write)

Wait for write completion (tQ5HQ5X)

AI02226B

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

SDP is Disabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Page Write

Timing

SDP is Enabled and

Application needs to Disable it

Time Out (tWLQ5H)

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

DATA has been written

and SDP is Disabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Page Write

Timing

SDP is Enabled and

Application needs to Write Data

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Physical

Write

Instructions

can be detected by reading the status of the Data
Polling and the Toggle Bit functions on DQ7 and
DQ6.
Page Write
The Page Write mode allows up to 128 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write
operations, no two of which are separated by more
than the t

WLQ5H

value (as specified in Table 9A to

Table 9C).
The page write can be initiated during any byte
write operation. Following the first Byte Write
instruction, the host may send another address
and data with a minimum data transfer rate of:
1/t

WLQ5H

The internal write cycle can start at any instant
after t

WLQ5H

. Once initiated, the write operation is

internally timed, and continues, uninterrupted,
until completion.
All bytes must be located on the same page
address (A16-A7 must be the same for all bytes).
Otherwise, the Page Write operation is not
executed. The Page Write Abort event is indicated
to the application via DQ1 (as described on page
8).
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-
protection mechanism that allows the user to
inhibit all write operations to the device, including
chip erase. This can be useful for protecting the

7/23

M28010

memory from inadvertent write cycles that may
occur during periods of instability (uncontrolled
bus conditions when excessive noise is detected,
or when power supply levels are outside their
specified values).
By

default,

the

device

shipped

the

"unprotected" state: the memory contents can be
freely changed by the user. Once the Software
Data Protection Mode is enabled, all write
commands are ignored, and have no effect on the
memory contents.
The device remains in this mode until a valid
Software Data Protection disable sequence is
received. The device reverts to its "unprotected"
state.
The status of the Software Data Protection
(enabled or disabled) is represented by a non-
volatile latch, and is remembered across periods
of the power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.

Similarly, to disable the Software Data Protection,
the user has to write specific data bytes into six
different locations, as shown in Figure 5. This
complex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex

(and

hence

better

protected

from

inadvertent use). The sequence is as shown in
Figure 5. This consists of an unlock key, to enable
the write action, at the end of which the SDP
continues to be enabled. This allows the SDP to
be enabled, and data to be written, within a single
Write cycle (t

Figure 6. Software Chip Erase Algorithm

Wait for write completion (tQ5HQ5X)

AI02236C

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

Whole Array has been Set to FFh

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 10h in

Address 5555h

Page Write

Timing

Time Out (tWLQ5H)

Figure 7. Status Bit Assignment

Figure 8. Software Data Protection Status Read
Algorithm

AI02486B

PLTS

PWA

SDP

DP
TB
PLTS
X
PWA
SDP

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

= Data Polling
= Toggle Bit
= Page Load Timer Status
= undefined
= Page Write Abort
= Software Data Protection

AI02237B

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Normal User Mode

Read SDP

on DQ0

Write xxh in

Address xxxxh

Page Write

Timing

M28010

8/23

Software Chip Erase
The device can be erased (with all bytes set to
FFh) by using a six-byte software command code.
This operation can be initiated only if the user
loads, with a Page Write addressing mode, six
specific data bytes to six specific locations (as
shown in Figure 6). The complexity of the
sequence has been designed to guard against
inadvertent use of the command.
Status Bits
The devices provide five status bits (DQ7, DQ6,
DQ5, DQ1 and DQ0) for use during write
operations. These allow the application to use the
write time latency of the device for getting on with
other work. These signals are available on the I/O
port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only
during the internal write cycle, t

Q5HQ5X

Data Polling bit (DQ7). The internally timed write
cycle starts as soon as t

WLQ5H

(defined in Table

9A to Table 9C) has elapsed since the previous
byte was latched in to the memory. The value of
the DQ7 bit of this last byte, is used as a signal
throughout this write operation: it is inverted while
the internal write operation is underway, and is
inverted back to its original value once the
operation is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
running. During the internal write cycle, DQ6
toggles from '0' to '1' and '1' to '0' (the first read
value being '0') on subsequent attempts to read
any byte of the memory. When the internal write
cycle is complete, the toggling is stopped, and the
values read on DQ7-DQ0 are those of the

addressed memory byte. This indicates that the
device is again available for new Read and Write
operations.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between
successive

Write operations,

WLQ5H

(defined in Table 9A to Table 9C). The DQ5 line is
held low to show when this timer is running (hence
showing that the device has received one write
operation, and is waiting for the next). The DQ5
line is held high when the counter has overflowed
(hence showing that the device is now starting the
internal write to the memory array).
Page Write Abort bit (DQ1). During a page write
operation, the A16 to A7 signals should be kept
constant.

They

should

not

change

while

successive data bytes are being transferred to the
internal latches of the memory device. If a change
occurs on any of the pins, A16 to A7, during the
page write operation (that is, before the falling
edge of W or E, which ever occurs later), the
internal write cycle is not started, and the internal
circuitry is completely reset.
The abort signal can be observed on the DQ1 pin,
using a normal read operation. This can be
performed at any time during the byte load cycle,
t

WLQ5H

, or while the W input is being held high

between two load cycles. The default value of DQ1
is initially set to '0' and changes to '1' if the internal
circuitry has detected a change on any of the
address pins A16 to A7. This PWA bit can be
checked regardless of whether Software Data
Protection is enabled or disabled.

Table 5A. Read Mode DC Characteristics for M28010 (5V range)
(T

= 40 to 85

C; V

= 4.5 to 5.5 V)

Note: 1. All inputs and outputs open circuit.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

0 V

Output Leakage Current

0 V

OUT

Supply Current (CMOS inputs)

E = V

, G = V

, f = 0.1 MHz

E = V

, G = V

, f = 5 MHz

E = V

, G = V

, f = 10 MHz

CC1

Supply Current (Stand-by) CMOS

E > V

0.3 V

Input Low Voltage

0.3

0.8

Input High Voltage

+ 0.3

Output Low Voltage

= 2.1 mA

0.4

Output High Voltage

= 400

2.4

9/23

M28010

Table 5B. Read Mode DC Characteristics for M28010-W (3V range)
(T

= 40 to 85

C; V

= 2.7 to 3.6 V)

Note: 1. All inputs and outputs open circuit.

Table 5C. Read Mode DC Characteristics for M28010-R (2V range)
(T

= 40 to 85

C; V

= 1.8 to 2.4 V)

Note: 1. All inputs and outputs open circuit.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

0 V

Output Leakage Current

0 V

OUT

Supply Current (CMOS inputs)

E = V

, G = V

, f = 0.1 MHz

E = V

, G = V

, f = 5 MHz

E = V

, G = V

, f = 10 MHz

CC1

Supply Current (Stand-by) CMOS

E > V

0.3 V

Input Low Voltage

0.3

0.6

Input High Voltage

+ 0.3

Output Low Voltage

= 1.6 mA

0.45

Output High Voltage

= 100

2.4

Symbol

Parameter

Test Conditio n

Min.

Max.

Unit

Input Leakage Current

0 V

Output Leakage Current

0 V

OUT

Supply Current (CMOS inputs)

E = V

, G = V

, f = 0.1 MHz, V

= 2.4 V

E = V

, G = V

, f = 5 MHz, V

= 2.4 V

CC1

Supply Current (Stand-by) CMOS

E > V

0.3 V

Input Low Voltage

0.3

0.2

Input High Voltage

0.3

+0.3

Output Low Voltage

= 0.4 mA

0.15

Output High Voltage

= 100

0.15

Software Data Protection bit (DQ0). Reading the
SDP bit (DQ0) allows the user to determine
whether the Software Data Protection mode has
been enabled (SDP=1) or disabled (SDP=0). The
SDP bit (DQ0) can be read by using a dedicated
algorithm (as shown in Figure 8), or can be
combined with the reading of the DP bit (DQ7), TB
bit (DQ6) and PLTS bit (DQ5).

M28010

10/23

Table 6. Input and Output Parameters

= 25

C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Capacitance

= 0 V

OUT

Output Capacitance

OUT

= 0 V

Table 7. AC Measurement Conditions

Input Rise and Fall Times

5 ns

Input Pulse Voltages

0 V to V

Input and Output Timing Ref. Voltages

Figure 9. AC Testing Input Output Waveforms

AI02228

VCC

VCC/2

Figure 10. AC Testing Equivalent Load Circuit

AI02578

OUT

CL = 30pF

CL includes JIG capacitance

IOL

DEVICE

UNDER

TEST

IOH

Table 8A. Read Mode AC Characteristics for M28010 (5V range)
(T

= 40 to 85

C; V

= 4.5 to 5.5 V)

Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Symbol

Alt.

Parameter

Test

Condi t

ion

M28010

Unit

10

12

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

G = V

100

120

ELQV

Chip Enable Low to Output Valid

G = V

100

120

GLQV

Output Enable Low to Output Valid

E = V

EHQZ

Chip Enable High to Output Hi-Z

G = V

GHQZ

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output
Transition

E = V

G = V

11/23

M28010

Table 8B. Read Mode AC Characteristics for M28010-W (3V range)
(T

= 40 to 85

C; V

= 2.7 to 3.6 V)

Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Table 8C. Read Mode AC Characteristics for M28010-R (2V range)
(T

= 40 to 85

C; V

= 1.8 to 2.4 V)

Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Symbol

Alt.

Parameter

Test

Condi t

ion

M28010-W

Unit

10

12

15

Min

Max

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

G = V

100

120

150

ELQV

Chip Enable Low to Output Valid

G = V

100

120

150

GLQV

Output Enable Low to Output Valid

E = V

100

EHQZ

Chip Enable High to Output Hi-Z

G = V

GHQZ

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output
Transition

E = V

G = V

Symbol

Alt.

Parameter

Test

Condi t

ion

M28010-R

Unit

20

25

Min

Max

Min

Max

AVQV

ACC

Address Valid to Output Valid

E = V

G = V

200

250

ELQV

Chip Enable Low to Output Valid

G = V

200

250

GLQV

Output Enable Low to Output Valid

E = V

EHQZ

Chip Enable High to Output Hi-Z

G = V

GHQZ

Output Enable High to Output Hi-Z

E = V

AXQX

Address Transition to Output
Transition

E = V

G = V

M28010

12/23

Table 9A. Write Mode AC Characteristics for M28010 (5V range)
(T

= 40 to 85

C; V

= 4.5 to 5.5 V)

Symbol

Alt.

Parameter

Test Condit ion

M28010

Unit

Min

Max

AVWL

Address Valid to Write Enable Low

E = V

, G = V

AVEL

Address Valid to Chip Enable Low

G = V

, W= V

ELWL

CES

Chip Enable Low to Write Enable Low

G = V

GHWL

OES

Output Enable High to Write Enable Low

E = V

GHEL

OES

Output Enable High to Chip Enable Low

W = V

WLEL

WES

Write Enable Low to Chip Enable Low

G = V

WLAX

Write Enable Low to Address Transition

ELAX

Chip Enable Low to Address Transition

ELEH

Chip Enable Low to Chip Enable High

100

WHEH

CEH

Write Enable High to Chip Enable High

WHGL

OEH

Write Enable High to Output Enable Low

EHWH

WEH

Chip Enable High to Write Enable High

WHDX

Write Enable High to Input Transition

EHDX

Chip Enable High to Input Transition

WHWL

WPH

Write Enable High to Write Enable Low

WLWH

Write Enable Low to Write Enable High

100

WLQ5H

BLC

Time-out after the last byte write

150

Q5HQ5X

Byte Write Cycle time

Page Write Cycle time (up to 128 bytes)

DVWH

Data Valid before Write Enable High

DVEH

Data Valid before Chip Enable High

Figure 11. Read Mode AC Waveforms (with Write Enable, W, high)

Note: 1. Write Enable (W) = V

AI02229

VALID

tAVQV

tAXQX

tGLQV

tEHQZ

tGHQZ

DATA OUT

A0-A16

DQ0-DQ7

tELQV

Hi-Z

13/23

M28010

Table 9B. Write Mode AC Characteristics for M28010-W (3V range)
(T

= 40 to 85

C; V

= 2.7 to 3.6 V)

Symbol

Alt.

Parameter

Test Condit ion

M28010-W

Unit

Min

Max

AVWL

Address Valid to Write Enable Low

E = V

, G = V

AVEL

Address Valid to Chip Enable Low

G = V

, W= V

ELWL

CES

Chip Enable Low to Write Enable Low

G = V

GHWL

OES

Output Enable High to Write Enable Low

E = V

GHEL

OES

Output Enable High to Chip Enable Low

W = V

WLEL

WES

Write Enable Low to Chip Enable Low

G = V

WLAX

Write Enable Low to Address Transition

ELAX

Chip Enable Low to Address Transition

ELEH

Chip Enable Low to Chip Enable High

100

WHEH

CEH

Write Enable High to Chip Enable High

WHGL

OEH

Write Enable High to Output Enable Low

EHWH

WEH

Chip Enable High to Write Enable High

WHDX

Write Enable High to Input Transition

EHDX

Chip Enable High to Input Transition

WHWL

WPH

Write Enable High to Write Enable Low

WLWH

Write Enable Low to Write Enable High

100

WLQ5H

BLC

Time-out after the last byte write

150

Q5HQ5X

Byte Write Cycle time

Page Write Cycle time (up to 128 bytes)

DVWH

Data Valid before Write Enable High

DVEH

Data Valid before Chip Enable High

M28010

14/23

Table 9C. Write Mode AC Characteristics for M28010-R (2V range)
(T

= 40 to 85

C; V

= 1.8 to 2.4 V)

Symbol

Alt.

Parameter

Test Condit ion

M28010-R

Unit

Min

Max

AVWL

Address Valid to Write Enable Low

E = V

, G = V

AVEL

Address Valid to Chip Enable Low

G = V

, W= V

ELWL

CES

Chip Enable Low to Write Enable Low

G = V

GHWL

OES

Output Enable High to Write Enable Low

E = V

GHEL

OES

Output Enable High to Chip Enable Low

W = V

WLEL

WES

Write Enable Low to Chip Enable Low

G = V

WLAX

Write Enable Low to Address Transition

120

ELAX

Chip Enable Low to Address Transition

120

ELEH

Chip Enable Low to Chip Enable High

120

WHEH

CEH

Write Enable High to Chip Enable High

WHGL

OEH

Write Enable High to Output Enable Low

EHWH

WEH

Chip Enable High to Write Enable High

WHDX

Write Enable High to Input Transition

EHDX

Chip Enable High to Input Transition

WHWL

WPH

Write Enable High to Write Enable Low

100

WLWH

Write Enable Low to Write Enable High

120

WLQ5H

BLC

Time-out after the last byte write

150

WHRH

Byte Write Cycle time

Page Write Cycle time (up to 128 bytes)

DVWH

Data Valid before Write Enable High

120

DVEH

Data Valid before Chip Enable High

120

M28010

18/23

Table 10. Ordering Information Scheme

Note: 1. This temperature range on request only.

Example:

M28010

Option

Tape & Reel Packing

Speed

-10

100 ns

Temperature Range

-12

120 ns

0 to 70

-15

150 ns

40 to 85

-20

200 ns

-25

250 ns

Operating Voltage

Package

blank 4.5 V to 5.5 V

PDIP32

2.7 V to 3.6 V

PLCC32

1.8 V to 2.4 V

TSOP32: 8 x 20mm

ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all `1's (FFh).
The notation used for the device number is as
shown in Table 10. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.

23/23

M28010

Information furnished is believed to be accurate and reliable. However, STMi croelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as criti cal components in life support devices or systems without express writt en approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http:// www.st.com

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M28010-20RKA1T

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M28010-20RKA1T