M28256

256 Kbit (32Kb x8) Parallel EEPROM

with Software Data Protection

PRELIMINARY DATA

January 1999

1/21

This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.

AI01885

A0-A14

DQ0-DQ7

VCC

M28256

VSS

Figure 1. Logic Diagram

PDIP28 (BS)

PLCC32 (KA)

A0-A14

Address Input

DQ0-DQ7

Data Input / Output

Write Enable

Chip Enable

Output Enable

Supply Voltage

Ground

Table 1. Signal Names

FAST ACCESS TIME:

90ns at 5V
120ns at 3V

SINGLE SUPPLY VOLTAGE:

10% for M28256

2.7V to 3.6V for M28256-xxW

LOW POWER CONSUMPTION
FAST WRITE CYCLE:

64 Bytes Page Write Operation
Byte or Page Write Cycle

ENHANCED END of WRITE DETECTION:

Data Polling
Toggle Bit

STATUS REGISTER
HIGH RELIABILITY DOUBLE POLYSILICON,

CMOS TECHNOLOGY:
Endurance >100,000 Erase/Write Cycles
Data Retention >10 Years

JEDEC APPROVED BYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION

DESCRIPTION
The M28256 and M28256-Ware 32K x8 low power
Parallel EEPROM fabricatedwith STMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.

TSOP28 (NS)

8 x13.4mm

SO28 (MS)

300 mils

DQ0

A13

A10

DQ7

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A12

A14

VCC

AI01886

M28256

Figure 2A. DIP Pin Connections

AI01887

A13

A10

DQ4

DQ0

DQ1

DQ2

DQ3

A14

A11

DQ6

DQ7

M28256

A12

DQ5

Figure 2B. LCC Pin Connections

Warning: NC = Not Connected, DU = Don't Use.

DQ0

A11

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A13

A12

A14

VCC

AI01889

M28256

VSS

A10

Figure 2D. TSOP Pin Connections

DQ0

DQ1

A10

A13

DQ7

DQ5

VCC

DQ4

A14

AI01888

M28256

DQ2

VSS

DQ6

A11

DQ3

A12

Figure 2C. SO Pin Connections

2/21

M28256

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(2)

40 to 85

STG

Storage Temperature Range

65 to 150

Supply Voltage

0.3 to 6.5

Input/Output Voltage

0.3 to V

+0.6

Input Voltage

0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

(3)

4000

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.

2. Depends on range.
3. 100pF through 1500

; MIL-STD-883C, 3015.7

Table 2. Absolute Maximum Ratings

(1)

AI01697

ADDRESS

LATCH

A6-A14

(Page Address)

DECODE

CONTROL LOGIC

256K ARRAY

ADDRESS

LATCH

A0-A5

Y DECODE

VPP GEN

RESET

SENSE AND DATA LATCH

I/O BUFFERS

PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING

DQ0-DQ7

Figure 3. Block Diagram

3/21

M28256

Mode

DQ0 - DQ7

Read

Data Out

Write

Data In

Standby / Write Inhibit

Hi-Z

Write Inhibit

Data Out or Hi-Z

Write Inhibit

Data Out or Hi-Z

Output Disable

Hi-Z

Notes: 1. X = V

or V

IL.

Table 3. Operating Modes

(1)

The devices offer fast access time with low power
dissipation and requires a 5V or 3V power supply.

The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation. A
Software Data Protection (SDP) is also possible
using the standard JEDEC algorithm.

PIN DESCRIPTION

Addresses (A0-A14). The address inputs select
an 8-bit memory location during a read or write
operation.

Chip Enable (E). The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.

Output Enable (G). The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.

Data In/ Out (DQ0- DQ7). Data is written to or read
from the memory through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the memory.

OPERATIONS

Write Protection

In order to prevent data corruption and inadvertent
write operations; an internal V

comparator inhib-

its Write operations if V

is below VWI (see Table

7 andTable 9).Access to the memory in write mode
is allowed after a power-up as specified in Table 7
and Table 9.

Read

The device is accessed like a static RAM. When E
and G are low with W high, the data addressed is
presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.

Write

Write operations are initiated when both W and E
are low and G is high.The device supports both E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accord-
ingly.

Page Write

Page write allows up to 64 bytes within the same
page to be consecutively latched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the same for all bytes; if not, the
Page Write instruction is not executed. The page
write can be initiated by any byte write operation.

A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the t

WHWH

value (see Table 12 and

Table 13).

If this period of time exceeds the t

WHWH

value, the

internal programmingcycle will start. Once initiated
the write operation is internally timed until comple-
tion and the status of the Data Polling and the
Toggle Bit functions on DQ7 and DQ6 is controlled
accordingly.

DESCRIPTION (Cont'd)

4/21

M28256

Status Register

The devices provide several Write operation status
flags that can be used to minimize the application
write time. These signals are available on the I/O
port bits during programming cycle only.

Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.

Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from "0" to "1" and "1" to "0" (the
first read value is "0") on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte. The device is now accessible for a new Read
or Write operation.

Page Load Timer Status bit (DQ5). Duringa Page
Write instruction, the devices expect to receive the
stream of data with a minimum period of time
between each data byte. This period of time
(t

WHWH

) is defined by the on-chip Page Load timer

which running/overflow status is available on DQ5.
DQ5 Low indicates that the timer is running, DQ5
High indicates the time-out after which the internal
write cycle will start.

Software Data Protection
The devices offer a software controlled write pro-
tection facility that allows the user to inhibit all write
modes to the device. This can be useful in protect-
ing the memory from inadvertent write cycles that
may occur due to uncontrolledbus conditions.
The devices are shipped as standardin the "unpro-
tected" state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device

enters the "Protect Mode" of

operation where no further write commands have
any effect on the memory contents.
The devices remain in this

mode until a valid

Software Data Protection (SDP) disable sequence
is received whereby the device reverts to its "un-
protected" state. The Software Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write (with a Page Write addressing three specific
data bytes to three specific memory locations,each
location in a different page) as per Figure 6. Simi-
larly to disable the Software Data Protection the
user has to write specific data bytes into six differ-
ent locations as per Figure 5 (with a Page Write
adressing different bytes in different pages).
This complexseries ensures that the userwill never
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
An extension to this is where SDP is required to be
set, and data is to be written.
Using the same sequence as above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (t

DQ7

DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

PLTS

= Data Polling

= Toggle Bit

PLTS = Page Load Timer Status

Figure 4. Status Bit Assignment

5/21

M28256

AI01698B

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE A0h in

Address 5555h

SDP is set

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE A0h in

Address 5555h

WRITE Data to

be Written in

any Address

SDP ENABLE ALGORITHM

Page
Write

Instruction

Page
Write

Instruction

WRITE
is enabled

SDP

Set

SDP

not Set

Write

in Memory

Write Data

SDP Set

after tWC

Figure 5. Software Data Protection Enable Algorithm and Memory Write

AI01699B

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE 80h in

Address 5555h

Unprotected State

after

tWC (Write Cycle time)

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE 20h in

Address 5555h

Page
Write

Instruction

Figure 6. Software Data Protection Disable Algorithm

6/21

M28256

Input Rise and Fall Times

20ns

Input Pulse Voltages (M28256)

0.4V to 2.4V

Input Pulse Voltages (M28256-W)

0V to V

0.3V

Input and Output Timing Ref. Voltages (M28256)

0.8V to 2.0V

Input and Output Timing Ref. Voltages (M28256-W)

0.5 V

Table 4. AC Measurement Conditions

AI02101B

4.5V to 5.5V Operating Voltage

2.7V to 3.6V Operating Voltage

VCC 0.3V

0.5 VCC

2.4V

0.4V

2.0V

0.8V

Figure 7. AC Testing Input Output Waveforms

AI02102B

OUT

CL = 100pF

CL includes JIG capacitance

IOL

DEVICE

UNDER

TEST

IOH

Figure 8. AC Testing Equivalent Load Circuit

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Note: 1. Sampled only, not 100% tested.

Table 5. Capacitance

(1)

= 25

C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

(1)

Supply Current (TTL inputs)

E = V

, G = V

, f = 5 MHz

Supply Current (CMOS inputs)

E = V

, G = V

, f = 5 MHz

CC1

(1)

Supply Current (Standby) TTL

E = V

CC2

(1)

Supply Current (Standby) CMOS

E > V

0.3V

100

Input Low Voltage

0.3

0.8

Input High Voltage

+ 0.5

Output Low Voltage

= 2.1 mA

0.4

Output High Voltage

= 400

2.4

Note: 1. All I/O's open circuit.

Table 6. Read Mode DC Characteristics for M28256
(T

= 0 to 70

C or 40 to 85

C; V

= 4.5V to 5.5V)

7/21

M28256

Symbol

Parameter

Min

Max

Unit

PUR

Time Delay to Read Operation

PUW

Time Delay to Write Operation (once V

)

Write Inhibit Threshold

3.0

4.2

Note: 1. Sampled only, not 100% tested.

Table 7. Power Up Timing for M28256

(1)

= 0 to 70

C or 40 to 85

C; V

= 4.5V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

(1)

Supply Current (CMOS inputs)

E = V

, G = V

, f = 5 MHz, V

= 3.3V

E = V

, G = V

, f = 5 MHz, V

= 3.6V

CC2

(1)

Supply Current (Standby) CMOS

E > V

0.3V

Input Low Voltage

0.3

0.6

Input High Voltage

+ 0.5

Output Low Voltage

= 2.1 mA

0.2 V

Output High Voltage

= 400

0.8 V

Note: 1. All I/O's open circuit.

Table 8. Read Mode DC Characteristics for M28256-W
(T

= 0 to 70

C or 40 to 85

C; V

= 2.7V to 3.6V)

Symbol

Parameter

Min

Max

Unit

PUR

Time Delay to Read Operation

PUW

Time Delay to Write Operation (once V

)

Write Inhibit Threshold

1.5

2.5

Note: 1. Sampled only, not 100% tested.

Table 9. Power Up Timing for M28256-W

(1)

= 0 to 70

C or 40 to 85

C; V

= 2.7V to 3.6V)

8/21

M28256

Symbol

Alt

Parameter

Test Condition

M28256

Unit

-90

-12

-15

-20

min

max

min

max

min

max

min

max

AVQV

ACC

Address Valid to
Output Valid

E = V

, G = V

120

150

200

ELQV

Chip Enable Low to
Output Valid

G = V

120

150

200

GLQV

Output Enable Low
to Output Valid

E = V

EHQZ

(1)

Chip Enable High to
Output Hi-Z

G = V

GHQZ

(1)

Output Enable High
to Output Hi-Z

E = V

AXQX

Address Transition
to Output Transition

E = V

, G = V

Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Table 10. Read Mode AC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 4.5V to 5.5V)

Symbol

Alt

Parameter

Test Condition

M28256-W

Unit

-12

-15

-20

-25

min

max

min

max

min

max

min

max

AVQV

ACC

Address Valid to
Output Valid

E = V

, G = V

120

150

200

250

ELQV

Chip Enable Low to
Output Valid

G = V

120

150

200

250

GLQV

Output Enable Low
to Output Valid

E = V

100

EHQZ

(1)

Chip Enable High to
Output Hi-Z

G = V

GHQZ

(1)

Output Enable High
to Output Hi-Z

E = V

AXQX

Address Transition
to Output Transition

E = V

, G = V

Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Table 11. Read Mode AC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 2.7V to 3.6V)

9/21

M28256

Symbol

Alt

Parameter

Test Condition

M28256

Unit

Min

Max

AVWL

Address Valid to Write Enable Low

E = V

, G = V

AVEL

Address Valid to Chip Enable Low

G = V

, W = V

ELWL

CES

Chip Enable Low to Write Enable Low

G = V

GHWL

OES

Output Enable High to Write Enable
Low

E = V

GHEL

OES

Output Enable High to Chip Enable Low

W = V

WLEL

WES

Write Enable Low to Chip Enable Low

G = V

WLAX

Write Enable Low to Address Transition

ELAX

Chip Enable Low to Address Transition

WLDV

Write Enable Low to Input Valid

E = V

, G = V

ELDV

Chip Enable Low to Input Valid

G = V

, W = V

ELEH

Chip Enable Low to Chip Enable High

WHEH

CEH

Write Enable High to Chip Enable High

WHGL

OEH

Write Enable High to Output Enable
Low

EHGL

OEH

Chip Enable High to Output Enable Low

EHWH

WEH

Chip Enable High to Write Enable High

WHDX

Write Enable High to Input Transition

EHDX

Chip Enable High to Input Transition

WHWL

WPH

Write Enable High to Write Enable Low

100

WLWH

Write Enable Low to Write Enable High

WHWH

BLC

Byte Load Repeat Cycle Time

0.15

150

WHRH

Write Cycle Time

, t

E or W Input Filter Pulse Width

Note 1

DVWH

Data Valid before Write Enable High

DVEH

Data Valid before Chip Enable High

Note: 1. Characterized only but not tested in production.

Table 12. Write Mode AC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 4.5V to 5.5V)

10/21

M28256

Symbol

Alt

Parameter

Test Condition

M28256-W

Unit

Min

Max

AVWL

Address Valid to Write Enable Low

E = V

, G = V

AVEL

Address Valid to Chip Enable Low

G = V

, W = V

ELWL

CES

Chip Enable Low to Write Enable Low

G = V

GHWL

OES

Output Enable High to Write Enable
Low

E = V

GHEL

OES

Output Enable High to Chip Enable Low

W = V

WLEL

WES

Write Enable Low to Chip Enable Low

G = V

WLAX

Write Enable Low to Address Transition

ELAX

Chip Enable Low to Address Transition

WLDV

Write Enable Low to Input Valid

E = V

, G = V

ELDV

Chip Enable Low to Input Valid

G = V

, W = V

ELEH

Chip Enable Low to Chip Enable High

100

WHEH

CEH

Write Enable High to Chip Enable High

WHGL

OEH

Write Enable High to Output Enable
Low

EHGL

OEH

Chip Enable High to Output Enable Low

EHWH

WEH

Chip Enable High to Write Enable High

WHDX

Write Enable High to Input Transition

EHDX

Chip Enable High to Input Transition

WHWL

WPH

Write Enable High to Write Enable Low

100

WLWH

Write Enable Low to Write Enable High

100

WHWH

BLC

Byte Load Repeat Cycle Time

0.2

150

WHRH

Write Cycle Time

, t

E or W Input Filter Pulse Width

Note 1

DVWH

Data Valid before Write Enable High

DVEH

Data Valid before Chip Enable High

Note: 1. Characterized only but not tested in production.

Table 13. Write Mode AC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 2.7V to 3.6V)

11/21

M28256

ORDERING INFORMATION SCHEME

Speed

(1)

90ns

120ns

150ns

200ns

(2)

250ns

Operating Voltage

blank

4.5V to 5.5V

2.7V to 3.6V

Package

BS PDIP28

KA PLCC32

MS SO28 300 mils

NS TSOP28

8 x 13.4mm

Temperature Range

(3)

0 to 70

40 to 85

Option

Tape & Reel
Packing

Example:

M28256 15

Notes: 1. Not available for "W" operating voltage.

2. Available for "W" operating voltage only.
3. Temperature Range on request only.

Devices are shipped from the factory with the memory content set at all "1's" (FFh).

For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

16/21

M28256

PLCC

E1 E

1 N

D2/E2

0.51 (.020)

1.14 (.045)

Symb

inches

Typ

Min

Max

Typ

Min

Max

2.54

3.56

0.100

0.140

1.52

2.41

0.060

0.095

0.38

0.015

0.33

0.53

0.013

0.021

0.66

0.81

0.026

0.032

12.32

12.57

0.485

0.495

11.35

11.56

0.447

0.455

9.91

10.92

0.390

0.430

14.86

15.11

0.585

0.595

13.89

14.10

0.547

0.555

12.45

13.46

0.490

0.530

1.27

0.050

0.00

0.25

0.000

0.010

0.89

0.035

Drawing is not to scale.

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

18/21

M28256

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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M28256

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M28256-25WBS1T