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PRELIMINARY DATA
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28C16B
M28C17B
16 Kbit (2K x 8) Parallel EEPROM
With Software Data Protection
s
Fast Access Time: 90 ns at V
CC
=5V
s
Single Supply Voltage:
4.5 V to 5.5 V for M28CxxB
2.7 V to 3.6 V for M28CxxB-W
s
Low Power Consumption
s
Fast BYTE and PAGE WRITE (up to 64 Bytes)
3 ms at V
CC
=4.5 V
5 ms at V
CC
=2.7 V
s
Enhanced Write Detection and Monitoring:
Data Polling
Toggle Bit
Page Load Timer Status
s
JEDEC Approved Bytewide Pin-Out
s
Software Data Protection
s
100000 Erase/Write Cycles (minimum)
s
Data Retention (minimum): 40 Years
DESCRIPTION
The M28C16B and M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabri-
cated with STMicroelectronics' proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation, and
require a single voltage supply.
Figure 1. Logic Diagram
AI02816
11
A0-A10
W
DQ0-DQ7
VCC
M28C16B
M28C17B
G
E
VSS
8
RB
(M28C17B only)
Table 1. Signal Names
A0-A10
Address Input
DQ0-DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready/Busy (M28C17B only)
V
CC
Supply Voltage
V
SS
Ground
PLCC32 (K)
M28C16B, M28C17B
2/17
Figure 2A. PLLC Connections
Note: 1. NC = Not Connected
AI02817
NC
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2
NC
DQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
NC
NC
DQ6
A7
DQ7
32
NC
V
CC
M28C16B
NC
NC
DQ5
G
E
25
V
SS
Figure 2B. PLLC Connections
Note: 1. NC = Not Connected
AI02830
NC
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2
NC
DQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
NC
NC
DQ6
A7
DQ7
32
RB
V
CC
M28C17B
NC
NC
DQ5
G
E
25
V
SS
The M28C17B is like the M28C16B in every way,
except that it has an extra ready/busy (RB) output.
The device has been designed to offer a flexible
microcontroller interface, featuring software hand-
shaking, with Data Polling and Toggle Bit. The de-
vice supports a 64 byte Page Write operation.
Software Data Protection (SDP) is also supported,
using the standard JEDEC algorithm.
SIGNAL DESCRIPTION
The external connections to the device are sum-
marized in Table 1, and their use in Table 3.
Addresses (A0-A10). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
Ready/Busy (RB). Ready/Busy (on the M28C17B
only) is an open drain output that can be used to
detect the end of the internal write cycle.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
CC
comparator in-
hibits the Write operations if the V
CC
voltage is
lower than V
WI
(see Table 4A). Once the voltage
applied on the V
CC
pin goes over the V
WI
thresh-
old (V
CC
>V
WI
), write access to the memory is al-
lowed after a time-out t
PUW
, as specified in Table
4A.
Further protection against data corruption is of-
fered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-
ter a delay, t
WLQ5H
, that cannot be shorter than the
value specified in Table 10A, the internal write cy-
cle starts. It continues, under internal timing con-
trol, until the write operation is complete. The
commencement of this period can be detected by
reading the Page Load Timer Status on DQ5. The
3/17
M28C16B, M28C17B
Figure 3. Block Diagram
AI02818
ADDRESS
LATCH
A6-A10
(Page Address)
X DECODE
CONTROL LOGIC
16K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPP GEN
RESET
SENSE AND DATA LATCH
I/O BUFFERS
E
G
W
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Table 2. Absolute Maximum Ratings
1
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
-40 to 125
C
T
STG
Storage Temperature
-65 to 150
C
V
CC
Supply Voltage
-0.3 to 6.5
V
V
IO
Input or Output Voltage
-0.6 to V
CC
+0.6
V
V
I
Input Voltage
-0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2
4000
V
M28C16B, M28C17B
4/17
Table 3. Operating Modes
1
Note: 1. 0=
V
IL
; 1=
V
IH
; X =
V
IH
or V
IL
; V=12V 5%.
Mode
E
G
W
DQ0-DQ7
Stand-by
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Chip Erase
0
V
0
Hi-Z
end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit func-
tions on DQ7 and DQ6.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
than the t
WLQ5H
value (as specified in Table 10A).
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
1/t
WLQ5H
.
The internal write cycle can start at any instant af-
ter t
WLQ5H
. Once initiated, the write operation is in-
ternally timed, and continues, uninterrupted, until
completion.
All bytes must be located on the same page ad-
dress (A10-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the "unprotect-
ed" state: the memory contents can be freely
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are
Table 4A. Power-Up Timing
1
for M28CxxB (5V range)
(T
A
= 0 to 70 C or -40 to 85 C; V
CC
= 4.5 to 5.5 V)
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing
1
for M28CxxB-W (3V range)
(T
A
= 0 to 70 C or -40 to 85 C; V
CC
= 2.7 to 3.6 V)
Note: 1. Sampled only, not 100% tested.
Symbol
Parameter
Min.
Max.
Unit
t
PUR
Time Delay to Read Operation
1
s
t
PUW
Time Delay to Write Operation (once V
CC
V
WI
)
10
ms
V
WI
Write Inhibit Threshold
3.0
4.2
V
Symbol
Parameter
Min.
Max.
Unit
t
PUR
Time Delay to Read Operation
1
s
t
PUW
Time Delay to Write Operation (once V
CC
V
WI
)
15
ms
V
WI
Write Inhibit Threshold
1.5
2.5
V
5/17
M28C16B, M28C17B
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its "unprotected"
state.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
ferent locations, as shown in Figure 6. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations.
AI02819
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
SDP is set
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
Page Write
(1 up to 64 bytes)
Write to Memory
When SDP is SET
SDP Enable Algorithm
Page Write
Timing
(see note 1)
Page Write
Timing
(see note 1)
Write
is Enabled
Physical
Page Write
Instruction
Figure 5. Status Bit Assignment
AI02815
DP
TB
PLTS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP
TB
PLTS
Hi-Z
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
= Data Polling
= Toggle Bit
= Page Load Timer Status
= High impedance
Figure 6. Software Data Protection Disable
Algorithm
AI02820
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write 80h in
Address 555h
Unprotected State
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write 20h in
Address 555h
Page Write
Timing
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