M28LV16
16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
November 1997
1/17
This is information on a product still in production bu t not recommended for new de sign.
AI01567B
11
A0-A10
W
DQ0-DQ7
VCC
M28LV16
G
E
VSS
8
RB *
Figure 1. Logic Diagram
A0 - A10
Address Input
DQ0 - DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready / Busy
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
FAST ACCESS TIME: 200ns
SINGLE LOW VOLTAGE OPERATION
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
64 Bytes Page Write Operation
Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
Data Polling
Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
Endurance >100,000 Erase/Write Cycles
Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28LV16 is replaced by the products
described on the document M28C16A
DESCRIPTION
The M28LV16 is a 2K x 8 low power Parallel
EEPROM fabricatedwith SGS-THOMSON proprie-
tary single polysilicon CMOS technology. The de-
vice offers fast access time with low power
dissipation and requires a 2.7V to 3.6V power
supply. The circuit has been designed to offer a
flexible microcontroller interface featuring both
hardware and software handshaking with Data
Polling and Toggle Bit. The M28LV16 supports 64
byte page write operation. A Software Data Protec-
tion (SDP) is also possible using the standard
JEDEC algorithm.
24
1
PDIP24 (P)
TSOP28 (N)
8 x 13.4mm
PLCC32 (K)
24
1
SO24 (MS)
300 mils
Note: * RB function is offered only with TSOP28 package.
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
A8
A9
DQ7
W
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
VCC
AI01568
M28LV16
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
AI01569B
NC
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2
DU
DQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
NC
NC
DQ6
A7
DQ7
32
DU
V
CC
M28LV16
NC
NC
DQ5
G
E
25
V
SS
Figure 2B. LCC Pin Connections
Warning: NC = Not Connected, DU = Don't Use.
DQ0
DQ1
A3
A0
A2
A1
A10
E
DQ7
G
DQ5
VCC
DQ4
A9
W
A4
A7
AI01570
M28LV16
8
2
3
4
5
6
7
9
10
11
12
22
21
20
19
18
17
16
15
DQ2
VSS
A6
A5
DQ6
24
23
DQ3
1
A8
16
15
Figure 2C. SO Pin Connections
A1
A0
DQ0
A5
A2
A4
A3
A9
NC
DQ7
A8
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
NC
W
NC
A6
RB
VCC
A7
AI01124C
M28LV16
28
1
22
7
8
14
15
21
VSS
A10
Figure 2D. TSOP Pin Connections
Warning: NC = Not Connected.
2/17
M28LV16
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 85
C
T
STG
Storage Temperature Range
65 to 150
C
V
CC
Supply Voltage
0.3 to 6.5
V
V
IO
Input/Output Voltage
0.3 to V
CC
+0.6
V
V
I
Input Voltage
0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
(2)
4000
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500
; MIL-STD-883C, 3015.7
Table 2. Absolute Maximum Ratings
(1)
Mode
E
G
W
DQ0 - DQ7
Standby
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Note: 1. 0 = V
IL
; 1 = V
IH
; X = V
IL
or V
IH
.
Table 3. Operating Modes
(1)
PIN DESCRIPTION
Addresses (A0-A10). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0 - DQ7). Data is written to or read
from the M28LV16 through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the M28LV16.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
It is offered only with the TSOP28 package. The
reader should refer to the M28LV17 datasheet
for more information about the Ready/Busy
function.
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset (POR) circuit resets all internal programming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specified in Table 7.
Read
The M28LV16 is accessed like a static RAM. When
E and G are low with W high, the data addressed
is presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28LV16 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
3/17
M28LV16
AI01520
ADDRESS
LATCH
A6-A10
(Page Address)
X
DECODE
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPP GEN
RESET
SENSE AND DATA LATCH
I/O BUFFERS
E
G
W
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure 3. Block Diagram
Page Write
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A10 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum data transfer rate of 1/t
WHWH
(see Figure 13).
If a transition of E or W is not detected within t
WHWH
,
the internal programming cycle will start.
Microcontroller Control Interface
The M28LV16 provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only.
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 4. Status Bit Assignment
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The M28LV16 offers another
way for determining when the internal write cycle
is completed. During the internal Erase/Write cycle,
DQ6 will toggle from "0" to "1" and "1" to "0" (the
first read value is "0") on subsequent attempts to
read the memory. When the internal cycle is com-
pleted the toggling will stop and the device will be
accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W. Up to
32 bytes may be input. The Data output (DQ5)
indicates the status of the internal Page Load
Timer. DQ5 may be read by asserting Output En-
able Low (t
PLTS
). DQ5 Low indicates the timer is
running, High indicates time-out after which the
write cycle will start and no new data may be input.
4/17
M28LV16
Software Data Protection
The M28LV16 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28LV16 is shipped as standard in the "unpro-
tected" state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the "Protect Mode" of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its "unprotected"
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
AI01509B
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
SDP is set
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
Write Page
(1 up to 64 bytes)
WRITE IN MEMORY
WHEN SDP IS SET
SDP ENABLE ALGORITHM
Page
Write
Instruction
(Note 1)
Page
Write
Instruction
(Note 1)
WRITE
is enabled
Figure 5. Software Data Protection Enable Algorithm and Memory Write
AI01510
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 80h in
Address 555h
Unprotected State
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 20h in
Address 555h
Page
Write
Instruction
Figure 6. Software Data Protection Disable
Algorithm
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
5/17
M28LV16
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 5. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
IN
V
CC
10
A
I
CC
(1)
Supply Current
(CMOS inputs)
E = V
IL
, G = V
IL
, f = 5 MHz, V
CC
= 3.3V
8
mA
E = V
IL
, G = V
IL
, f = 5 MHz, V
CC
= 3.6V
10
mA
I
CC2
(1)
Supply Current (Standby)
CMOS
E > V
CC
0.3V
50
A
V
IL
Input Low Voltage
0.3
0.6
V
V
IH
Input High Voltage
2
V
CC
+0.5
V
V
OL
Output Low Voltage
I
OL
= 1 mA
0.2 V
CC
V
V
OH
Output High Voltage
I
OH
= 1 mA
0.8 V
CC
V
Note: 1. All I/O's open circuit.
Table 6. Read Mode DC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 2.7V to 3.6V)
Symbol
Parameter
Min
Max
Unit
t
PUR
Time Delay to Read Operation
1
s
t
PUW
Time Delay to Write Operation
10
ms
V
WI
Write Inhibit Threshold
1.5
2.5
V
Note: 1. Sampled only, not 100% tested.
Table 7. Power Up Timing
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 2.7V to 3.6V)
Input Rise and Fall Times
20ns
Input Pulse Voltages
0V to V
CC
-0.3V
Input and Output Timing Ref.
Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01274
VCC 0.3V
0V
0.5 VCC
Figure 7. AC Testing Input Output Waveforms
AI01396
VCC
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1.3k
Figure 8. AC Testing Equivalent Load Circuit
6/17
M28LV16
Symbol
Alt
Parameter
Test Condition
M28LV16
Unit
-200
-250
-300
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output
Valid
E = V
IL
, G = V
IL
200
250
300
ns
t
ELQV
t
CE
Chip Enable Low to Output
Valid
G = V
IL
200
250
300
ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E = V
IL
100
150
150
ns
t
EHQZ
(1)
t
DF
Chip Enable High to Output
Hi-Z
G = V
IL
0
55
0
60
0
60
ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
0
55
0
60
0
60
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 8. Read Mode AC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 2.7V to 3.6V)
AI01511B
VALID
tAVQV
tAXQX
tGLQV
tEHQZ
tGHQZ
DATA OUT
A0-A10
E
G
DQ0-DQ7
tELQV
Hi-Z
Figure 9. Read Mode AC Waveforms
Note: Write Enable (W) = High
7/17
M28LV16
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVWL
t
AS
Address Valid to Write Enable Low
E = V
IL
, G = V
IH
0
ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
G = V
IH
, W = V
IL
0
ns
t
ELWL
t
CES
Chip Enable Low to Write Enable Low
G = V
IH
0
ns
t
GHWL
t
OES
Output Enable High to Write Enable
Low
E = V
IL
0
ns
t
GHEL
t
OES
Output Enable High to Chip Enable Low
W = V
IL
0
ns
t
WLEL
t
WES
Write Enable Low to Chip Enable Low
G = V
IH
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
100
ns
t
ELAX
t
AH
Chip Enable Low to Address Transition
100
ns
t
WLDV
t
DV
Write Enable Low to Input Valid
E = V
IL
, G = V
IH
1
s
t
ELDV
t
DV
Chip Enable Low to Input Valid
G = V
IH
, W = V
IL
1
s
t
ELEH
t
WP
Chip Enable Low to Chip Enable High
100
1000
ns
t
WHEH
t
CEH
Write Enable High to Chip Enable High
0
ns
t
WHGL
t
OEH
Write Enable High to Output Enable
Low
0
ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low
0
ns
t
EHWH
t
WEH
Chip Enable High to Write Enable High
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
ns
t
EHDX
t
DH
Chip Enable High to Input Transition
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
50
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
100
ns
t
WHWH
t
BLC
Byte Load Repeat Cycle Time
0.2
100
s
t
WHRH
t
WC
Write Cycle Time
3
ms
t
DVWH
t
DS
Data Valid before Write Enable High
50
ns
t
DVEH
t
DS
Data Valid before Chip Enable High
50
ns
Table 9. Write Mode AC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 2.7V to 3.6V)
8/17
M28LV16
AI01521
VALID
tAVWL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tWLAX
tELWL
tGHWL
tWLDV
tWHEH
tWHGL
tWLWH
tWHWL
tWHDX
tDVWH
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
AI01522
VALID
tAVEL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tELAX
tGHEL
tWLEL
tELDV
tEHGL
tEHDX
tDVEH
tELEH
tEHWH
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
9/17
M28LV16
AI01523
A0-A10
E
G
DQ0-DQ7
W
tWHWH
Addr 0
DQ5
Addr 1
Addr 2
Addr n
tWHWH
tWHRH
tWLWH
tWHWL
tPLTS
Byte 0
Byte 1
Byte 2
Byte n
Byte n
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
AI01515
A0-A5
E
G
DQ0-DQ7
W
tWLWH
tDVWH
Byte 0
tWHWL
A6-A10
tWLAX
tWHWH
tWHDX
tAVEL
555h
2AAh
555h
Byte 62
Byte 63
AAh
55h
A0h
Byte Address
Page Address
Figure 13. Software Protected Write Cycle Waveforms
Note: A6 through A10 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
10/17
M28LV16
AI01516
A0-A10
E
G
DQ7
W
DQ7
DQ7
DQ7
DQ7
DQ7
READY
LAST WRITE
INTERNAL WRITE SEQUENCE
Address of the last byte of the Page Write instruction
Figure 14. Data Polling Waveform Sequence
AI01517
A0-A10
E
G
DQ6
W
READY
LAST WRITE
INTERNAL WRITE SEQUENCE
(1)
TOGGLE
Figure 15. Toggle Bit Waveform Sequence
Note: 1. First Toggle bit is forced to '0'
11/17
M28LV16
ORDERING INFORMATION SCHEME
Notes: 1. The M28LV16 in TSOP28 package has a Ready/Busy output on pin 1.
2. Packages available on request only.
Devices are shipped from the factory with the memory content set at all "1's" (FFh).
For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the SGS-THOMSON Sales Office nearest to you.
Speed
-200
200ns
-250
250ns
-300
300ns
Package
P
(2)
PDIP24
K
PLCC32
MS
(2)
SO24 300mils
N
(1)
TSOP28
8 x 13.4mm
Temperature Range
1
0 to 70
C
6
40 to 85
C
Option
T
Tape & Reel
Packing
Example:
M28LV16
-200 K
1
T
12/17
M28LV16
PDIP
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
3.94
5.08
0.155
0.200
A1
0.38
1.78
0.015
0.070
A2
3.56
4.06
0.140
0.160
B
0.38
0.56
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.30
0.008
0.012
D
32.26
1.270
E
14.80
16.26
0.583
0.640
E1
12.50
13.97
0.492
0.550
e1
2.54
0.100
eA
15.20
17.78
0.598
0.700
L
3.05
3.82
0.120
0.150
S
1.02
2.29
0.040
0.090
0
15
0
15
N
24
24
PDIP24
Drawing is not to scale.
PDIP24 - 24 pin Plastic DIP, 600 mils width
13/17
M28LV16
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
j
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
2.54
3.56
0.100
0.140
A1
1.52
2.41
0.060
0.095
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
e
1.27
0.050
j
0.89
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
PLCC32
Drawing is not to scale.
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
14/17
M28LV16
SO-b
E
N
CP
B
e
A2
D
C
L
A1
1
H
A
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
2.46
2.64
0.097
0.104
A1
0.13
0.29
0.005
0.011
A2
2.29
2.39
0.090
0.094
B
0.35
0.48
0.014
0.019
C
0.23
0.32
0.009
0.013
D
15.20
15.60
0.598
0.614
E
7.42
7.59
0.292
0.299
e
1.27
0.050
H
10.16
10.41
0.400
0.410
L
0.61
1.02
0.024
0.040
0
8
0
8
N
24
24
CP
0.10
0.004
SO24
Drawing is not to scale.
SO24 - 24 lead Plastic Small Outline, 300 mils body width
15/17
M28LV16
TSOP-c
D1
E
7
8
CP
B
e
A2
A
22
D
DIE
C
L
A1
21
28
1
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
1.25
0.049
A1
0.20
0.008
A2
0.95
1.15
0.037
0.045
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.20
13.60
0.520
0.535
D1
11.70
11.90
0.461
0.469
E
7.90
8.10
0.311
0.319
e
0.55
0.022
L
0.50
0.70
0.020
0.028
0
5
0
5
N
28
28
CP
0.10
0.004
TSOP28
Drawing is not to scale.
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
16/17
M28LV16
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
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M28LV16
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