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Электронный компонент: M28C64X-150P1

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M28C64C
M28C64X
64 Kbit (8Kb x8) Parallel EEPROM
February 1999
1/15
AI00746B
13
A0-A12
W
DQ0-DQ7
VCC
M28C64C
G
E
VSS
8
RB
Figure 1. Logic Diagram
28
1
PDIP28 (P)
PLCC32 (K)
A0 - A12
Address Input
DQ0 - DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready / Busy
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
FAST ACCESS TIME: 150ns
SINGLE 5V
10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE
32 Bytes Page Write Operation
Byte or Page Write Cycle: 5ms
ENHANCED END OF WRITE DETECTION
Ready/Busy Open Drain Output
(for M28C64C product only)
Data Polling
Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY
Endurance >100,000 Erase/Write Cycles
Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
DESCRIPTION
The M28C64C is an 8 Kbit x8 low power Parallel
EEPROM fabricated with STMicroelectronics pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 5V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshakingmode with Ready/Busy,
Data Polling and Toggle Bit. The M28C64C sup-
ports 32 byte page write operation.
TSOP28 (N)
8 x13.4mm
28
1
SO28 (MS)
300 mils
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
DU
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
RB
VCC
AI00747C
M28C64C
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
Warning: DU = Don't Use.
AI00748D
DU
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2
DU
DQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
RB
A11
DQ6
A7
DQ7
32
DU
V
CC
M28C64C
A12
NC
DQ5
G
E
25
V
SS
Figure 2B. LCC Pin Connections
Warning: NC = Not Connected, DU = Don't Use.
A1
A0
DQ0
A5
A2
A4
A3
A9
A11
DQ7
A8
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
DU
W
A12
A6
RB
VCC
A7
AI01016D
M28C64C
28
1
22
7
8
14
15
21
VSS
A10
Figure 2D. TSOP Pin Connections
Warning: DU = Don't Use.
DQ0
DQ1
A3
A0
A2
A1
A10
E
DU
DQ7
G
DQ5
VCC
DQ4
A9
W
A4
RB
A7
AI00876C
M28C64C
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
DQ2
VSS
A6
A5
DQ6
28
27
26
25
24
23
A11
DQ3
1
A12
A8
Figure 2C. SO Pin Connections
Warning: DU = Don't Use.
PIN DESCRITPION
Addresses (A0-A12).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
2/15
M28C64C, M28C64X
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
STG
Storage Temperature Range
65 to 150
C
V
CC
Supply Voltage
0.3 to 6.5
V
V
IO
Input/Output Voltage
0.3 to V
CC
+0.6
V
V
I
Input Voltage
0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2000
V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Mode
E
G
W
DQ0 - DQ7
Read
V
IL
V
IL
V
IH
Data Out
Write
V
IL
V
IH
V
IL
Data In
Standby / Write Inhibit
V
IH
X
X
Hi-Z
Write Inhibit
X
X
V
IH
Data Out or Hi-Z
Write Inhibit
X
V
IL
X
Data Out or Hi-Z
Output Disable
X
V
IH
X
Hi-Z
Note: X = V
IH
or V
IL
Table 3. Operating Modes
Data In/ Out (DQ0 - DQ7). Data is written to or read
from the M28C64C through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the M28C64C.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset (POR) circuit resets all internal programming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specified in Table 6.
Read
The M28C64C is accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pins are high impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28C64C supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A5 - A12 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data up to a maxi-
mum of 100
s after the rising edge of E or W which
ever occurs first (t
BLC
). If a transition of E or W is
not detected within 100
s, the internal program-
ming cycle will start.
3/15
M28C64C, M28C64X
AI00877C
ADDRESS
LATCH
A5-A12
(Page Address)
X
DECODE
ATD & CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
A0-A4
Y DECODE
VPP GEN
RESET
SENSE AND DATA LATCH
I/O BUFFERS
RB
E
G
W
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure 3. Block Diagram
Microcontroller Control Interface
The M28C64C provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
DQ7
DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 4. Status Bit Assignment
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The M28C64C offers another
way for determining when the internal write cycle
is completed. Duringthe internal Erase/Write cycle,
DQ6 will toggle from "0" to "1" and "1" to "0" (the
first read value is "0") on subsequent attempts to
read any address in the memory. When the internal
cycle is completed the toggling will stop and the
device will be accessible for a new Read or Write
operation.
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W up to
100
s after the previous byte. Up to 32 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (t
PLTS
).
DQ5 Low indicates the timer is running,
High
indicates time-out after which the write cycle will
start and no new data may be input.
Ready/Busy pin. The RB pin provides a signal at
its open drain output which is low during the
erase/write cycle, but which is released at the
completion of the programming cycle.
4/15
M28C64C, M28C64X
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 5. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
IN
V
CC
10
A
I
CC
(1)
Supply Current (TTL and CMOS inputs)
E = V
IL
, G = V
IL
, f = 5 MHz
30
mA
I
CC1
(1)
Supply Current (Standby) TTL
E = V
IH
2
mA
I
CC2
(1)
Supply Current (Standby) CMOS
E > V
CC
0.3V
100
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2
V
CC
+0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= 400
A
2.4
V
Note: 1. All I/O's open circuit.
Table 6. Read Mode DC Characteristics (T
A
= 0 to 70
C or 40 to 85
C, V
CC
= 4.5V to 5.5V)
Symbol
Parameter
Min
Max
Unit
t
PUR
Time Delay to Read Operation
1
s
t
PUW
Time Delay to Write Operation
10
ms
Note: 1. Sampled only, not 100% tested.
Table 7. Power Up Timing
(1)
(T
A
= 0 to 70
C or 40 to 85
C, V
CC
= 4.5V to 5.5V)
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.4V to 2.4V
Input and Output Timing Ref. Voltages
0.8V to 2.0V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI00826
2.4V
0.4V
2.0V
0.8V
Figure 5. AC Testing Input Output Waveforms
AI01129
1.3V
OUT
CL = 30pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 6. AC Testing Equivalent Load Circuit
5/15
M28C64C, M28C64X