AI02078C

A0-A17

DQ0-DQ7

VCC

M29F002T
M29F002B

M29F002NT

VSS

(*) RPNC

Figure 1. Logic Diagram

M29F002T, M29F002NT

M29F002B

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

NOT FOR NEW DESIGN

M29F002T, M29F002NT and M29F002B are
replaced respectively by the M29F002BT,
M29F002BNT and M29F002BB.
5V

10% SUPPLY VOLTAGE for PROGRAM,

ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10

s typical

PROGRAM/ERASE CONTROLLER (P/E.C.)
Program Byte-by-Byte
Status Register bits
MEMORY BLOCKS
Boot Block (Top or Bottom location)
Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
Read and Program another Block during

Erase Suspend

LOW POWER CONSUMPTION
Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code, M29F002T: B0h
Device Code, M29F002NT: B0h
Device Code, M29F002B: 34h

DESCRIPTION
The M29F002 is a non-volatile memory that may be
erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 5V V

supply. For Program and

Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in

July 2000

1/29

This is information on a product still in production but not recommended for new design.

PLCC32 (K)

PDIP32 (P)

TSOP32 (N)

8 x 20mm

Note: * RPNC function is not available for the M29F002NT

AI02079C

A17

A13

A10

DQ5

DQ0

DQ1

DQ2

DQ3

DQ4

A16

DQ7

A12

A14

RPNC

M29F002T
M29F002B

A15

A11

DQ6

Figure 2B. LCC Pin Connections

DQ0

A13

A10

DQ7

A14

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A17

A16

A12

(*) RPNC

VCC

A15

AI02080C

M29F002T
M29F002B

M29F002NT

Figure 2A. DIP Pin Connections

DQ0

A13

A10

DQ7

A14

A11

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A17

A16

A12

RPNC

VCC

A15

AI02361B

M29F002T
M29F002B

VSS

Figure 2C. TSOP Pin Connections

Note: Pin 1 is not connected for the M29F002NT

A0-A17

Address Inputs

DQ0-DQ7

Data Input/Outputs, Command Inputs

Chip Enable

Output Enable

Write Enable

RPNC

(*)

Reset / Block Temporary Unprotect

Supply Voltage

Ground

Table 1. Signal Names

DESCRIPTION (cont'd)

the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for reading
the Electronic Signature or Block Protection status,
Programming, Block and Chip Erase, Erase Sus-
pend and Resume are written to the device in
cycles of commands to a Command Interface using
standard microprocessor write timings. The device
is offered in PLCC32, PDIP32 and TSOP32 (8 x 20
mm) packages.

2/29

M29F002T, M29F002NT, M29F002B

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 125

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltages

0.6 to 7

Supply Voltage

0.6 to 7

(A9, E, G, RPNC)

(2)

A9, E, G, RPNC Voltage

0.6 to 13.5

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns.
3. Depends on range.

Table 2. Absolute Maximum Ratings

(1)

Organisation

The M29F002 is organised as 256K x 8. Memory
control is provided by Chip Enable E, Output Enable
G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RPNC
(NOT available on M29F002NT) tri-level input pro-
vides a hardware reset when pulled Low, and when
held High (at V

) temporarily unprotects blocks

previously protected allowing them to be progra-
med and erased. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on DQ7
provides a Data Polling signal, and DQ6 and DQ2
provide Toggle signals to indicate the state of the
P/E.C operations.

Memory Blocks

The devices feature asymmetrically blocked archi-
tecture providing system memory integration. The
M29F002 has an array of 7 blocks, one Boot Block
of 16 KBytes, two Parameter Blocks of 8 KBytes,
one Main Block of 32 KBytes and three Main Blocks
of 64 KBytes.

The memory map is shown in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read

from or program to any block not being ersased,
and then resumed. Block protection provides addi-
tional data security. Each block can be separately
protected or unprotected against Program or Erase
on programming equipment. All previously pro-
tected blocks can be temporarily unprotected in the
application.

Bus Operations

The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t e ct io n, Un pr o te c ti on, P r ot ec t ion Ver if y,
Unprotection Verify and Block Temporary Unprotec-
tion. See Tables 4 and 5.

Command Interface

Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Command'
itself and its confirmation, when applicable, are
given on the third, fourth or sixth cycles. Any incor-
rect command or any improper command se-
quence will reset the device to Read Array mode.

3/29

M29F002T, M29F002NT, M29F002B

Address Range

A17

A16

A15

A14

A13

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-37FFFh

38000h-39FFFh

3A000h-3BFFFh

3C000h-3FFFFh

Table 3A. M29F002T, M29F002NT Block Address Table

Address Range

A17

A16

A15

A14

A13

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

Table 3B. M29F002B Block Address Table

AI02081C

16K BOOT BLOCK

3FFFFh

3C000h

3BFFFh

3A000h

39FFFh

00000h

8K PARAMETER BLOCK

32K MAIN BLOCK

64K MAIN BLOCK

M29F002T, M29F002NT

38000h

37FFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

00000h

8K PARAMETER BLOCK

32K MAIN BLOCK

64K MAIN BLOCK

M29F002B

10000h

0FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

16K BOOT BLOCK

Figure 3. Memory Map and Block Address Table

4/29

M29F002T, M29F002NT, M29F002B

Instructions

Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing
and verification of the Program and Erase opera-
tions. The Status Register Data Polling, Toggle,
Error bits may be read at any time, during program-
ming or erase, to monitor the progress of the opera-
tion.

Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instruc-
tions (see Table 8). The third cycle inputs the in-
struction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.

When power is first applied or if V

falls below

LKO

, the command interface is reset to Read Array.

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A17). The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to V

, either a Read

Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.

Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high

impedance when the chip is deselected or the
outputs are disabled and when RPNC is at a Low
level.

Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V

during the Block Unprotection opera-

tion.

Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V

level during

Block Protection and Unprotection operations.

Write Enable (W). This input controls writing to the
Command Register and Address and Data latches.

Reset/Block Temporary Unprotect/No Connect
Input (RPNC). The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection func-
tions. In read or write mode, the RPNC pin can be
left open (Not Connected) or held at V

. Reset of

the memory is acheived by pulling RPNC to V

for

at least 500ns. When the reset pulse is given, if the
memory is in Read or Standby modes, it will be
available for new operations in 50ns after the rising
edge of RPNC. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
10

s. A hardware reset during an Erase or Program

operation will corrupt the data being programmed
or the sector(s) being erased.

Temporary block unprotection is made by holding
RPNC at V

. In this condition previously protected

blocks can be programmed or erased. The transi-
tion of RPNC from V

to V

must slower than

500ns. When RPNC is returned from V

to V

all

blocks temporarily unprotected will be again pro-
tected.

Supply Voltage. The power supply for all op-

erations (Read, Program and Erase).

Ground. V

is the reference for all voltage

measurements.

DEVICE OPERATIONS

See Tables 4, 5 and 6.

Read. Read operations are used to output the con-
tents of the Memory Array, the Electronic Signature,
the Status Register or the Block Protection Status.
Both Chip Enable E and Output Enable G must be
low in order to read the output of the memory.

5/29

M29F002T, M29F002NT, M29F002B

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