1/22

April 2002

M29F002BT, M29F002BNT

M29F002BB, M29F002BNB

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

SINGLE 5V ± 10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 45 ns

PROGRAMMING TIME

8 µs by Byte typical

7 MEMORY BLOCKS

1 Boot Block (Top or Bottom Location)

2 Parameter and 4 Main Blocks

PROGRAM/ERASE CONTROLLER

Embedded Byte Program algorithm

Embedded Multi-Block/Chip Erase algorithm

Status Register Polling and Toggle Bits

ERASE SUSPEND and RESUME MODES

Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

Faster Production/Batch Programming

TEMPORARY BLOCK UNPROTECTION
MODE

LOW POWER CONSUMPTION

Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per
BLOCK

20 YEARS DATA RETENTION

Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Top Device Code M29F002BT: B0h

Top Device Code M29F002BNT: B0h

Bottom Device Code M29F002BB: 34h

Bottom Device Code M29F002BNB: 34h

TSOP32 (N)

8 x 20mm

PLCC32 (K)

PDIP32 (P)

Figure 1. Logic Diagram

AI02957B

A0-A17

DQ0-DQ7

VCC

M29F002BT
M29F002BB

M29F002BNT
M29F002BNB

VSS

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

2/22

Figure 2. PLCC Connections

AI02959B

A17

A13

A10

DQ5

DQ0

DQ1

DQ2

DQ3

DQ4

A16

DQ7

A12

A14

M29F002BT
M29F002BB

M29F002BNB

A15

A11

DQ6

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

M29F002BT, M29F002BB:
Reset/Block Temporary Unprotect

M29F002BNT, M29F002BNB:
Not Connected Internally

Supply Voltage

Ground

Figure 3. TSOP Connections

DQ0

A13

A10

DQ7

A14

A11

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A17

A16

A12

VCC

A15

AI02958

M29F002BT
M29F002BB

VSS

Figure 4. PDIP Connections

DQ0

A13

A10

DQ7

A14

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A17

A16

A12

VCC

A15

AI02960

M29F002BT
M29F002BB

M29F002BNT

3/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

SUMMARY DESCRIPTION
The M29F002B is a 2 Mbit (256Kb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM. The
M29F002B is fully backward compatible with the
M29F002.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

°C

Ambient Operating Temperature (Temperature Range Option 6)

40 to 85

°C

Ambient Operating Temperature (Temperature Range Option 3)

40 to 125

°C

BIAS

Temperature Under Bias

50 to 125

°C

STG

Storage Temperature

65 to 150

°C

(2)

Input or Output Voltage

0.6 to 6

Supply Voltage

0.6 to 6

Identification Voltage

0.6 to 13.5

Table 4. Bottom Boot Block Addresses,
M29F002BB

Size

(Kbytes)

Address Range

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 20mm),
PLCC32 and PDIP packages and it is supplied
with all the bits erased (set to '1').

Table 3. Top Boot Block Addresses,
M29F002BT, M29F002BNT

Size

(Kbytes)

Address Range

3C000h-3FFFFh

3A000h-3BFFFh

38000h-39FFFh

30000h-37FFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

4/22

SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected. On the M29F002BNT the pin is not
connected internally and this feature is not avail-
able.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

or t

PLYH

, whichever occurs last. See Table 15 and

Figure 12, Reset/Temporary Unprotect AC Char-
acteristics for more details.
Holding RP at V

will temporarily unprotect the

protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V

to V

must be slower than

PHPHH

Reset/Block Temporary Unprotect can be left un-
connected. A weak internal pull-up resistor en-
sures that the memory always operates correctly.

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,
V

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

CC4

Ground. The V

Ground is the reference for

all voltage measurements.

5/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 5. Bus Operations

Note: X = V

or V

Operation

Address Inputs

Data

Inputs/Outputs

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

20h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

B0h (M29F002BT)

B0h (M29F002BNT)

34h (M29F002BB)

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 5, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see Figure 9, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.

When Chip Enable is at V

the Supply Current is

reduced to the TTL Standby Supply Current, I

CC2

To further reduce the Supply Current to the CMOS
Standby Supply Current, I

CC3

, Chip Enable should

be held within V

± 0.2V. For Standby current

levels see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC4

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the CMOS Standby Supply Current, I

CC3

The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V

to be applied to some pins.

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 5, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.

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