1/21

April 2000

M29F080A

8 Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory

SINGLE 5V

10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 70ns

PROGRAMMING TIME

s by Byte typical

16 UNIFORM 64 Kbyte MEMORY BLOCKS

PROGRAM/ERASE CONTROLLER

Embedded Byte Program algorithm

Embedded Multi-Block/Chip Erase algorithm

Status Register Polling and Toggle Bits

Ready/Busy Output Pin

ERASE SUSPEND and RESUME MODES

Read and Program another Block during

Erase Suspend

TEMPORARY BLOCK UNPROTECTION
MODE

LOW POWER CONSUMPTION

Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per
BLOCK

20 YEARS DATA RETENTION

Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Device Code: F1h

TSOP40 (N)

10 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI00501C

A0-A19

DQ0-DQ7

VCC

M29F080A

VSS

M29F080A

2/21

Figure 2. TSOP Connections

DQ1

DQ2

A10

A14

A17

A18

DQ7

A13

A19

DQ5

DQ3

VSS

VCC

DQ4

DQ6

A12

A11

VCC

AI00520B

M29F080A

A15

A16

VSS

DQ0

Figure 3. SO Connections

A17

A18

A19

A16

DQ6

DQ2

VSS

VCC

VSS

DQ4

A13

VCC

A10

AI00521B

M29F080A

DQ0

DQ1

DQ7

A15

A14

DQ3

DQ5

A11

A12

Table 1. Signal Names

A0-A19

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Supply Voltage

Ground

Not Connected Internally

SUMMARY DESCRIPTION
The M29F080A is an 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-

ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected in groups to prevent accidental Program
or Erase commands from modifying the memory.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in a TSOP40 (10 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to '1').

3/21

M29F080A

SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

Ambient Operating Temperature (Temperature Range Option 6)

40 to 85

Ambient Operating Temperature (Temperature Range Option 3)

40 to 125

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage

0.6 to 6

Supply Voltage

0.6 to 6

Identification Voltage

0.6 to 13.5

Table 3. Uniform Block Addresses, M29F080A

Size

(Kbytes)

Address Range

Protection

Group

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

M29F080A

4/21

A 0.1

F capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

CC4

Ground. The V

Ground is the reference for

all voltage measurements.

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

RHEL

, whichever occurs last. See the Ready/Busy

Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V

will temporarily unprotect the

protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V

. Ready/Busy will remain Low during

Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,
V

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.

5/21

M29F080A

Table 4. Bus Operations

Note: X = V

or V

Operation

Address Inpu ts

Data

Inputs/Outpu ts

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

20h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

F1h

Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at V

the Supply Current is

reduced to the TTL Standby Supply Current, I

CC2

To further reduce the Supply Current to the CMOS
Standby Supply Current, I

CC3

, Chip Enable should

be held within V

0.2V. For Standby current

levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC4

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

0.2V)

are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I

CC3

. The

Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V

to be applied to some pins.

Electronic Signature. The

memory

has

two

codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection and Blocks Unprotection. Blocks
can be protected in groups against accidental Pro-
gram or Erase. See Table 3, Block Addresses, for
details of which blocks must be protected together
as a group. Protected blocks can be unprotected
to allow data to be changed. Block Protection and
Block Unprotection operations must only be per-
formed on programming equipment.
For further information refer to Application Note
AN1122, Applying Protection and Unprotection to
M29 Series Flash.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M29F080A-70M6T

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M29F080A-70M6T