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March 2000

M29W008AT

M29W008AB

8 Mbit (1Mb x8, Boot Block)

Low Voltage Single Supply Flash Memory

2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 80ns

PROGRAMMING TIME: 10µs typical

PROGRAM/ERASE CONTROLLER (P/E.C.)

Program Byte-by-Byte

Status Register bits and Ready/Busy Output

SECURITY PROTECTION MEMORY AREA

INSTRUCTIONS ADDRESS CODING: 3 digits

MEMORY BLOCKS

Boot Block (Top or Bottom location)

Parameter and Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES

ERASE SUSPEND and RESUME MODES

Read and Program another Block during

Erase Suspend

LOW POWER CONSUMPTION

Stand-by and Automatic Stand-by

100,000 PROGRAM/ERASE CYCLES per
BLOCK

20 YEARS DATA RETENTION

Defectivity below 1ppm/year

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Top Device Code, M29W008AT: D2h

Bottom Device Code, M29W008AB: DCh

Figure 1. Logic Diagram

AI02716

A0-A19

DQ0-DQ7

VCC

M29W008AT
M29W008AB

VSS

TSOP40 (N)

10 x 20mm

M29W008AT, M29W008AB

2/30

Figure 2. TSOP Connections

VSS

DQ1

DQ2

A11

A17

A14

A15

DQ7

A16

DQ5

DQ3

VCC

DQ4

DQ6

A18

AI02717

M29W008AT
M29W008AB

A12

A13

A19

A10

VCC

DQ0

VSS

Table 1. Signal Names

A0-A19

Address Inputs

DQ0-DQ7

Data Input/Outputs, Command Inputs

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Supply Voltage

Ground

Not Connected Internally

Organisation
The M29W008A is organised as 1Mb x8. The
memory uses the address inputs A0-A19 and the
Data Input/Outputs DQ0-DQ7. Memory control is
provided by Chip Enable E, Output Enable G and
Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-lev-
el input provides a hardware reset when pulled
Low, and when held High (at V

) temporarily un-

protects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W008AT and M29W008AB devices have an
array of 19 blocks, one Boot Block of 16 Kbytes,
two Parameter Blocks of 8 Kbytes, one Main Block
of 32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008AT has the Boot Block at the top of
the memory address space and the M29W008AB
locates the Boot Block starting at the bottom. The
memory maps are showed in Tables 3, 4. Each
block can be erased separately, any combination
of blocks can be specified for multi-block erase or
the entire chip may be erased. The Erase opera-
tions are managed automatically by the P/E.C.

DESCRIPTION
The M29W008A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V V

supply. For

Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the de-
vice in cycles of commands to a Command Inter-
face using standard microprocessor write timings.
The device is offered in TSOP40 (10 x 20mm)
package.

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M29W008AT, M29W008AB

Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume. The internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits and the RB output may be
read at any time, during programming or erase, to
monitor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In or-
der to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruc-
tion, the fourth command cycle inputs the address
and data to be programmed. For an Erase instruc-
tion (Block or Chip), the fourth and fifth cycles in-
put a further Coded sequence before the Erase
confirm command on the sixth cycle. Erasure of a
memory block may be suspended, in order to read
data from another block or to program data in an-
other block, and then resumed.
When power is first applied or if V

falls below V

L-

, the command interface is reset to Read Array.

The block erase operation can be suspended in
order to read from or program to any block not be-
ing erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature, Block Protection Status), Write com-
mand, Output Disable, Stand-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro-
tection Verify and Block Temporary Unprotection.
See Tables 5 and 6.
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Com-
mand' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.
3. Depends on range.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 85

°C

BIAS

Temperature Under Bias

50 to 125

°C

STG

Storage Temperature

65 to 150

°C

(2)

Input or Output Voltage

0.6 to 5

Supply Voltage

0.6 to 5

(A9, E, G, RP)

(2)

A9, E, G, RP Voltage

0.6 to 13.5

M29W008AT, M29W008AB

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Table 3. Top Boot Block Addresses,
M29W008AT

Size

(Kbytes)

Address Range

FC000h-FFFFFh

FA000h-FBFFFh

F8000h-F9FFFh

F0000h-F7FFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

Table 4. Bottom Boot Block Addresses,
M29W008AB

Size

(Kbytes)

Address Range

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

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M29W008AT, M29W008AB

SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W. When A9 is raised to V

, either a

Read Electronic Signature Manufacturer or Device
Code, Block Protection Status or a Write Block
Protection or Block Unprotection is enabled de-
pending on the combination of levels on A0, A1
A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is
data to be programmed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip Enable E or Write En-
able W. The output is data from the Memory Array,
the Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high im-
pedance when the chip is deselected or the out-
puts are disabled and when RP is at a Low level.

Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the stand-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level. The Chip
Enable must be forced to V

during the Block Un-

protection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance. G must be forced to V

level during

Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.

Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction.
When RB is High, the device is ready for any
Read, Program or Erase operation. The RB will
also be High when the memory is put in Erase
Suspend or Stand-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
V

for at least t

PLPX

. When the reset pulse is giv-

en, if the memory is in Read or Stand-by modes, it
will be available for new operations in t

PHEL

after

the rising edge of RP.
If the memory is in Erase, Erase Suspend or Pro-
gram modes the reset will take t

PLYH

during which

the RB signal will be held at V

. The end of the

memory reset will be indicated by the rising edge
of RB. A hardware reset during an Erase or Pro-
gram operation will corrupt the data being pro-
grammed or the sector(s) being erased. See
Tables 15, 16 and Figure 8.
Temporary block unprotection is made by holding
RP at V

. In this condition previously protected

blocks can be programmed or erased. The transi-
tion of RP from V

to V

must slower than t

PH-

PHH

. (See Tables 17, 18 and Figure 8). When RP

is returned from V

to V

all blocks temporarily

unprotected will be again protected.
V

Supply Voltage. The power supply for all

operations (Read, Program and Erase).
V

Ground. V

is the reference for all voltage

measurements.

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