AI02189
20
A0-A19
W
DQ0-DQ7
VCC
M29W008T
M29W008B
E
VSS
8
G
RP
RB
Figure 1. Logic Diagram
M29W008T
M29W008B
8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W008T and M29W008B are replaced
respectively by the M29W008AT and
M29W008AB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10
s typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
Program Byte-by-Byte
Status Register bits and Ready/Busy Output
MEMORY BLOCKS
Boot Block (Top or Bottom location)
Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code, M29W008T: D2h
Device Code, M29W008B: DCh
DESCRIPTION
The M29W008 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V V
CC
supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
June 1999
1/30
This is information on a product still in production but not recommended for new designs.
TSOP40 (N)
10 x 20 mm
VSS
DQ1
DQ2
A7
A1
E
A4
A3
A11
A17
A14
A15
DQ7
A9
A16
G
NC
DQ5
DQ3
NC
VCC
DQ4
DQ6
A8
W
RB
A18
NC
RP
AI02190
M29W008T
M29W008B
10
1
11
20
21
30
31
40
A0
A12
A13
A19
A10
A5
A6
VCC
DQ0
VSS
A2
Figure 2. TSOP Pin Connections
A0-A19
Address Inputs
DQ0-DQ7
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset / Block Temporary Unprotect
RB
Ready/Busy Output
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
Warning: NC = Not Connected.
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commands to a Command Interface using
standard microprocessor write timings. The device
is offered in TSOP40 (10 x 20mm) package.
Organisation
The M29W008 is organised as 1Mb x 8. The mem-
ory uses the address inputs A0-A19 and the Data
Input/Outputs DQ0-DQ7. Memory control is pro-
vided by Chip Enable E, Output Enable G and Write
Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
ID
) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
DESCRIPTION (Cont'd)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 85
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltages
0.6 to 5
V
V
CC
Supply Voltage
0.6 to 5
V
V
(A9, E, G, RP)
(2)
A9, E, G, RP Voltage
0.6 to 13.5
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns.
3. Depends on range.
Table 2. Absolute Maximum Ratings
(1)
2/30
M29W008T, M29W008B
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W008T and M29W008B devices have an array
of 19 blocks, one Boot Block of 16 Kbytes, two
Parameter Blocks of 8 Kbytes, one Main Block of
32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008T has the Boot Block at the top of
the memory address space and the M29W008B
locates the Boot Block starting at the bottom. The
memory maps are showed in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t e c t i on , U n pr ot e c t ion , Pr o t ec t ion Ve r if y,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Com-
mand' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations. The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if Vcc falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to V
ID
, either a Read
Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RP is at a Low level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V
ID
during the Block Unprotection opera-
tion.
3/30
M29W008T, M29W008B
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