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M29W017D

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TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 16. Block Addresses, M29W017D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M29W017D

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSOP40 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 24

TSOP40 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 24

TFBGA48 8x9mm 6x8 active ball array 0.80mm pitch, Bottom View Package Outline . . . . . . 25

TFBGA48 8x9mm 6x8 active ball array 0.80mm pitch, Package Mechanical Data . . . . . . . . . 25

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M29W017D

4/36

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Block Addresses, M29W017D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Programmer Technique Bus Operations, BYTE = V

or V

. . . . . . . . . . . . . . . . . . . . . 31

Figure 14. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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M29W017D

SUMMARY DESCRIPTION
The M29W017D is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.

The memory is divided into 32 blocks of 64KBytes
(see Table 16, Block Addresses) that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory is
supplied with all the bits erased (set to '1').

Figure 2. Logic Diagram

Table 1. Signal Names

AI04186

A0-A20

DQ0-DQ7

VCC

M29W017D

VSS

A0-A20

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Supply Voltage

Ground

Not Connected Internally

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M29W017D

SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

RHEL

, whichever occurs last. See the Ready/Busy

Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V

will temporarily unprotect the

protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.

The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V

. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 13 and Figure
13, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V

Supply Voltage (2.7V to 3.6V). V

pro-

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,
V

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between
the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power
supply. See Figure 10, AC Measurement Load Cir-
cuit. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

CC3

Ground. V

is the reference for all voltage

measurements.

M29W017D

10/36

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typical-
ly glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the
Standby Supply Current, I

CC2

, Chip Enable should

be held within V

± 0.2V. For the Standby current

level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC3

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I

CC2

. The

Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V

to be applied to some pins.

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in Appendix C.

Table 2. Bus Operations

Note: X = V

or V

Operation

Address Inputs

A0-A20

Data Inputs/Outputs

DQ7-DQ0

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

20h

Read Device Code

A0 = V

, A1 = V

A9 = V

, Others V

or V

C8h

11/36

M29W017D

COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.

Refer to Table 3, Commands, in conjunction with
the following text descriptions.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V

and A1 = V

. The other address bits

may be set to either V

or V

. The Manufacturer

Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = V

and A1 = V

. The other

address bits may be set to either V

or V

. The

Device Code for the M29W017D is C8h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V

A1 = V

, and A16-A20 specifying the address of

the block. The other address bits may be set to ei-
ther V

or V

. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.

If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at '0' back to '1'. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from '0' to '1'.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in the memory array at a
time. The command requires two Bus Write oper-
ations, the final write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset

M29W017D

12/36

command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to '1'. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend

command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to '1'. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being is-
sued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume. During
Erase Suspend it is possible to Read and Program
cells in blocks that are not being erased; both
Read and Program operations behave as normal
on these blocks. If any attempt is made to program
in a protected block or in the suspended block then
the Program command is ignored and the data re-
mains unchanged. The Status Register is not read
and no error condition is given. Reading from
blocks that are being erased will output the Status
Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The de-
vice must be in Read Array mode before the Re-
sume command will be accepted. An erase can be
suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is in the Read

13/36

M29W017D

Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect-
ed mode.

See Appendix B, Tables 17, 18, 19, 20, 21 and 22
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.

Block Protect and Chip Unprotect operations are
described in Appendix C.

Table 3. Commands

Note: x Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

Command

Leng

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

Auto Select

Program

Unlock Bypass

Unlock Bypass
Program

Unlock Bypass Reset

Chip Erase

Block Erase

Erase Suspend

Erase Resume

Read CFI Query

M29W017D

14/36

Table 4. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. T

= 25°C, V

= 3.3V.

STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 5, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts '0', the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a '1' during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a '0' to a '1' when the Program/Erase
Controller has suspended the Erase operation.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from '0' to '1' to '0', etc., with succes-

sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to '1' when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to '0' back to '1' and attempting to do so will
set DQ5 to `1'. A Bus Read operation to that ad-
dress will show the bit is still `0'. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from '0' to '1'.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to '1'. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to '0' and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.

Parameter

Min

Typ

(1)

Typical after

100k W/E Cycles

(1)

Max

Unit

Chip Erase

120

Block Erase (64 KBytes)

0.8

Program (Byte)

200

µs

Chip Program (Byte by Byte)

120

Program/Erase Cycles (per Block)

100,000

cycles

15/36

M29W017D

Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from '0' to '1' to '0', etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from '0' to '1' to '0', etc. with successive

Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from '0' to
'1' to '0', etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.

Table 5. Status Register Bits

Note: Unspecified data bits should be ignored.

Operation

Address

DQ7

DQ6

DQ5

DQ3

DQ2

Program

Any Address

DQ7

Toggle

Program During Erase
Suspend

Any Address

DQ7

Toggle

Program Error

Any Address

DQ7

Toggle

Chip Erase

Any Address

Toggle

Block Erase before
timeout

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Block Erase

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Erase Suspend

Erasing Block

No Toggle

Toggle

Non-Erasing Block

Data read as normal

Erase Error

Good Block Address

Toggle

No Toggle

Faulty Block Address

Toggle

M29W017D

18/36

DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.

Table 7. Operating and AC Measurement Conditions

Figure 8. AC Measurement I/O Waveform

Figure 9. AC Measurement Load Circuit

Table 8. Device Capacitance

Note: Sampled only, not 100% tested.

Parameter

M29W017D

Unit

Min

Max

Min

Max

Supply Voltage

3.0

3.6

2.7

3.6

Ambient Operating Temperature

°C

Load Capacitance (C

)

100

Input Rise and Fall Times

Input Pulse Voltages

0 to V

Input and Output Timing Ref. Voltages

AI05254

VCC

VCC/2

AI05255

CL includes JIG capacitance

DEVICE

UNDER

TEST

25k

VCC

25k

VCC

0.1µF

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

M29W017D

20/36

Figure 10. Read AC Waveforms

Table 10. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

M29W017D

Unit

AVAV

Address Valid to Next Address Valid

E = V

G = V

Min

AVQV

ACC

Address Valid to Output Valid

E = V

G = V

Max

ELQX

(1)

Chip Enable Low to Output Transition

G = V

Min

ELQV

Chip Enable Low to Output Valid

G = V

Max

GLQX

(1)

OLZ

Output Enable Low to Output
Transition

E = V

Min

GLQV

Output Enable Low to Output Valid

E = V

Max

EHQZ

(1)

Chip Enable High to Output Hi-Z

G = V

Max

GHQZ

(1)

Output Enable High to Output Hi-Z

E = V

Max

EHQX

GHQX

AXQX

Chip Enable, Output Enable or
Address Transition to Output Transition

Min

AI05248

tAVAV

tAVQV

tAXQX

tELQX

tEHQZ

tGLQV

tGLQX

tGHQX

VALID

A0-A20

DQ0-DQ7

tELQV

tEHQX

tGHQZ

VALID

21/36

M29W017D

Figure 11. Write AC Waveforms, Write Enable Controlled

Table 11. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

M29W017D

Unit

AVAV

Address Valid to Next Address Valid

Min

ELWL

Chip Enable Low to Write Enable Low

Min

WLWH

Write Enable Low to Write Enable High

Min

DVWH

Input Valid to Write Enable High

Min

WHDX

Write Enable High to Input Transition

Min

WHEH

Write Enable High to Chip Enable High

Min

WHWL

WPH

Write Enable High to Write Enable Low

Min

AVWL

Address Valid to Write Enable Low

Min

WLAX

Write Enable Low to Address Transition

Min

GHWL

Output Enable High to Write Enable Low

Min

WHGL

OEH

Write Enable High to Output Enable Low

Min

WHRL

(1)

BUSY

Program/Erase Valid to RB Low

Max

VCHEL

VCS

High to Chip Enable Low

Min

µs

AI05249

A0-A20

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWH

tGHWL

tWHRL

M29W017D

22/36

Figure 12. Write AC Waveforms, Chip Enable Controlled

Table 12. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

M29W017D

Unit

AVAV

Address Valid to Next Address Valid

Min

WLEL

Write Enable Low to Chip Enable Low

Min

ELEH

Chip Enable Low to Chip Enable High

Min

DVEH

Input Valid to Chip Enable High

Min

EHDX

Chip Enable High to Input Transition

Min

EHWH

Chip Enable High to Write Enable High

Min

EHEL

CPH

Chip Enable High to Chip Enable Low

Min

AVEL

Address Valid to Chip Enable Low

Min

ELAX

Chip Enable Low to Address Transition

Min

GHEL

Output Enable High Chip Enable Low

Min

EHGL

OEH

Chip Enable High to Output Enable Low

Min

EHRL

(1)

BUSY

Program/Erase Valid to RB Low

Max

VCHWL

VCS

High to Write Enable Low

Min

µs

AI05250

A0-A20

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEH

tGHEL

tEHRL

M29W017D

26/36

PART NUMBERING

Table 14. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to '1'.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

REVISION HISTORY

Table 15. Document Revision History

Example:

M29W017D

Device Type
M29

Operating Voltage

W = V

= 2.7 to 3.6V

Device Function
017D = 16 Mbit (x8), Uniform Block

Speed

70 = 70 ns
90 = 90 ns

Package

N = TSOP40: 10 x 20 mm
ZA = TFBGA48: 0.80mm pitch

Temperature Range
1 = 0 to 70 °C

6 = 40 to 85 °C

Option
T = Tape & Reel Packing

Date

Version

Revision Details

May-2001

-01

First Issue (Brief Data)

18-Jun-2001

-02

Document expanded to full Product Preview, TFBGA Package Mechanical changed.

26-Jul-2001

-03

Document type: from Product Preview to Preliminary Data

03-Dec-2001

-04

Block Protection Appendix added, Read/Reset operation during Erase Suspend clarified .

05-Apr-2002

-05

Description of Ready/Busy signal clarified (and Figure 13 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section

M29W017D

28/36

APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure

is read from the memory. Tables 17, 18, 19, 20, 21
and 22 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 22, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read/
Reset command to return to Read mode.

Table 17. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 18. CFI Query Identification String

Address

Sub-section Name

Description

10h

CFI Query Identification String

Command set ID and algorithm data offset

1Bh

System Interface Information

Device timing & voltage information

27h

Device Geometry Definition

Flash device layout

40h

Primary Algorithm-specific Extended Query
table

Additional information specific to the Primary
Algorithm (optional)

61h

Security Code Area

64 bit unique device number

Address

Data

Description

Value

10h

51h

"Q"

11h

52h

Query Unique ASCII String "QRY"

"R"

12h

59h

"Y"

13h

02h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm

AMD

Compatible

14h

00h

15h

40h

Address for Primary Algorithm extended Query table (see Table 20)

P = 40h

16h

00h

17h

00h

Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported

18h

00h

19h

00h

Address for Alternate Algorithm extended Query table

1Ah

00h

29/36

M29W017D

Table 19. CFI Query System Interface Information

Table 20. Device Geometry Definition

Address

Data

Description

Value

1Bh

27h

Logic Supply Minimum Program/Erase voltage

bit 7 to 4

BCD value in volts

bit 3 to 0

BCD value in 100 mV

2.7V

1Ch

36h

Logic Supply Maximum Program/Erase voltage

bit 7 to 4

BCD value in volts

bit 3 to 0

BCD value in 100 mV

3.6V

1Dh

00h

[Programming] Supply Minimum Program/Erase voltage

1Eh

00h

[Programming] Supply Maximum Program/Erase voltage

1Fh

04h

Typical timeout per single byte/word program = 2

µs

16µs

20h

00h

Typical timeout for minimum size write buffer program = 2

µs

21h

0Ah

Typical timeout per individual block erase = 2

22h

00h

Typical timeout for full chip erase = 2

23h

04h

Maximum timeout for byte/word program = 2

times typical

256µs

24h

00h

Maximum timeout for write buffer program = 2

times typical

25h

03h

Maximum timeout per individual block erase = 2

times typical

26h

00h

Maximum timeout for chip erase = 2

times typical

Address

Data

Description

Value

27h

15h

Device Size = 2

in number of bytes

2 MByte

28h
29h

00h
00h

Flash Device Interface Code description

Async.

2Ah
2Bh

00h
00h

Maximum number of bytes in multi-byte program or page = 2

2Ch

01h

Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.

2Dh
2Eh

1Fh
00h

Region 1 Information
Number of identical size erase block = 001Fh+1

2Fh
30h

00h
01h

Region 1 Information
Block size in Region 1 = 0100h * 256 byte

64 KByte

31/36

M29W017D

APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the tech-
niques for AMD parts will not work on STMicro-
electronics parts. Care should be taken when
changing drivers for one part to work on another.
Programmer Technique
The Programmer technique uses high (V

) volt-

age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 14,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to pro-
tect all of the blocks first, then all blocks can be un-
protected at the same time. To unprotect the chip
follow Figure 15, Programmer Equipment Chip
Unprotect Flowchart. Table 23, Programmer

Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash has been fitted to the sys-
tem.
To protect a block follow the flowchart in Figure 16,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig-
ure 17, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.

Table 23. Programmer Technique Bus Operations, BYTE = V

or V

Operation

Address Inputs

A0-A20

Data Inputs/Outputs

DQ15A1, DQ14-DQ0

Block Protect

Pulse

A9 = V

, A12-A20 Block Address

Others = X

Chip Unprotect

Pulse

A9 = V

, A12 = V

, A15 = V

Others = X

Block Protection
Verify

A0 = V

, A1 = V

, A6 = V

, A9 = V

A12-A20 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection
Verify

A0 = V

, A1 = V

, A6 = V

, A9 = V

A12-A20 Block Address

Others = X

Retry = XX01h

Pass = XX00h

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