M29W160ET, M29W160EB

2/40

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Bus Operations, BYTE = V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bus Operations, BYTE = V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M29W160ET, M29W160EB

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Commands, 16-bit mode, BYTE = V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Commands, 8-bit mode, BYTE = V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 17

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15.TSOP48 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 26

Table 16. TSOP48 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26

Figure 16.TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline . . . . . . . . . . . . . . . 27

Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M29W160ET, M29W160EB

4/40

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Top Boot Block Addresses, M29W160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Bottom Boot Block Addresses, M29W160EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 27. Programmer Technique Bus Operations, BYTE = V

or V

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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M29W160ET, M29W160EB

SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.

The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The

command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to '1').

Figure 2. Logic Diagram

Table 1. Signal Names

AI06849B

A0-A19

DQ0-DQ14

VCC

M29W160ET
M29W160EB

VSS

DQ15A1

BYTE

A0-A19

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

Data Inputs/Outputs

DQ15A1

Data Input/Output or Address Input

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

BYTE

Byte/Word Organization Select

Supply Voltage

Ground

Not Connected Internally

M29W160ET, M29W160EB

10/40

SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the Program/
Erase Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V

. When BYTE is Low, V

, these pins

are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V

, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V

, this pin behaves as an address

pin; DQ15A1 Low will select the LSB of the Word
on the other addresses, DQ15A1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

RHEL

, whichever occurs last. See the Ready/Busy

Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V

will temporarily unprotect the

protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V

. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, V

, the memory is in 8-bit mode, when

it is High, V

, the memory is in 16-bit mode.

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,
V

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

CC3

Ground. The V

Ground is the reference for

all voltage measurements. The two V

pins of the

device must be connected to the system ground.

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M29W160ET, M29W160EB

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the
Standby Supply Current, I

CC2

, Chip Enable should

be held within V

± 0.2V. For the Standby current

level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC3

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I

CC2

. The

Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require V

to be

applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.

Table 2. Bus Operations, BYTE = V

Note: X = V

or V

Operation

Address Inputs

DQ15A1, A0-A19

Data Inputs/Outputs

DQ14-DQ8

DQ7-DQ0

Bus Read

Cell Address

Hi-Z

Data Output

Bus Write

Command Address

Hi-Z

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

20h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

C4h (M29W160ET)

49h (M29W160EB)

M29W160ET, M29W160EB

12/40

Table 3. Bus Operations, BYTE = V

Note: X = V

or V

COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.

Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V

and A1 = V

. The other address bits

may be set to either V

or V

. The Manufacturer

Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = V

and A1 = V

. The other

address bits may be set to either V

or V

. The

Device Code for the M29W160ET is 22C4h and
for the M29W160EB is 2249h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V

A1 = V

, and A12-A19 specifying the address of

the block. The other address bits may be set to ei-
ther V

or V

. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data, and starts
the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory returns to the Read mode, unless an error

Operation

Address Inputs

A0-A19

Data Inputs/Outputs

DQ15A1, DQ14-DQ0

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

0020h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

22C4h (M29W160ET)

2249h (M29W160EB)

13/40

M29W160ET, M29W160EB

has occurred. When an error occurs the memory
continues to output the Status Register. A Read/
Reset command must be issued to reset the error
condition and return to Read mode.
Note that the Program command cannot change a
bit set at '0' back to '1'. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from '0' to '1'.

Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.

Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data,
and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to '1'. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 6. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in
the unprotected selected blocks to '1'. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a

M29W160ET, M29W160EB

14/40

Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time (refer to Table 6
for value) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.

Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is in the Read
Array mode, or when the device is in Auto Select
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.
See Appendix B, Tables 21, 22, 23, 24, 25 and 26
for details on the information contained in the
Common Flash Interface (CFI) memory area.

15/40

M29W160ET, M29W160EB

Table 4. Commands, 16-bit mode, BYTE = V

Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.
The Command Interface only uses A1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don't
Care. DQ15A1 is A1 when BYTE is V

or DQ15 when BYTE is V

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-
gram/Erase Controller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in Auto Select mode.

Command

ngth

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

555

2AA

Auto Select

555

2AA

555

Program

555

2AA

555

Unlock Bypass

555

2AA

555

Unlock Bypass
Program

Unlock Bypass Reset

Chip Erase

555

2AA

555

2AA

555

Block Erase

555

2AA

555

2AA

Erase Suspend

Erase Resume

Read CFI Query

M29W160ET, M29W160EB

16/40

Table 5. Commands, 8-bit mode, BYTE = V

Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.
The Command Interface only uses A1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don't
Care. DQ15A1 is A1 when BYTE is V

or DQ15 when BYTE is V

Command

ngth

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

AAA

555

Auto Select

AAA

555

AAA

Program

AAA

555

AAA

Unlock Bypass

AAA

555

AAA

Unlock Bypass
Program

Unlock Bypass Reset

Chip Erase

AAA

555

AAA

555

AAA

Block Erase

AAA

555

AAA

555

Erase Suspend

Erase Resume

Read CFI Query

17/40

M29W160ET, M29W160EB

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V

after 100,000 program/erase cycles .

4. Maximum value measured at worst case conditions for both temperature and V

STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts '0', the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a '1' during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a '0' to a '1' when the Program/Erase
Controller has suspended the Erase operation.
Figure 7, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from '0' to '1' to '0', etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 8, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to '1' when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.

Parameter

Min

Typ

(1,2)

Max

(2)

Unit

Chip Erase

120

(3)

Block Erase (64 KBytes)

0.8

(4)

Erase Suspend Latency Time

(4)

µs

Program (Byte or Word)

200

(3)

µs

Chip Program (Byte by Byte)

120

(3)

Chip Program (Word by Word)

(3)

Program/Erase Cycles (per Block)

100,000

cycles

Data Retention

years

M29W160ET, M29W160EB

18/40

Note that the Program command cannot change a
bit set to '0' back to '1' and attempting to do so will
set DQ5 to `1'. A Bus Read operation to that ad-
dress will show the bit is still `0'. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from '0' to '1'
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to '1'. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to '0' and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.

During Chip Erase and Block Erase operations the
Toggle Bit changes from '0' to '1' to '0', etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from '0' to '1' to '0', etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from '0' to
'1' to '0', etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Operation

Address

DQ7

DQ6

DQ5

DQ3

DQ2

Program

Any Address

DQ7

Toggle

Program During Erase
Suspend

Any Address

DQ7

Toggle

Program Error

Any Address

DQ7

Toggle

Chip Erase

Any Address

Toggle

Block Erase before
timeout

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Block Erase

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Erase Suspend

Erasing Block

No Toggle

Toggle

Non-Erasing Block

Data read as normal

Erase Error

Good Block Address

Toggle

No Toggle

Faulty Block Address

Toggle

19/40

M29W160ET, M29W160EB

Figure 7. Data Polling Flowchart

Figure 8. Data Toggle Flowchart

MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at

these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.

Table 8. Absolute Maximum Ratings

Note: 1. Minimum voltage may undershoot to 2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V

+2V during transition and for less than 20ns during transitions.

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL

PASS

AI03598

DQ7

DATA

YES

DQ5

= 1

DQ7

DATA

YES

READ DQ6

START

READ DQ6

TWICE

FAIL

PASS

AI01370C

DQ6

TOGGLE

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Symbol

Parameter

Min

Max

Unit

BIAS

Temperature Under Bias

125

°C

STG

Storage Temperature

150

°C

Input or Output Voltage

(1,2)

0.6

+0.6

Supply Voltage

0.6

Identification Voltage

0.6

13.5

M29W160ET, M29W160EB

20/40

DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.

Table 9. Operating and AC Measurement Conditions

Figure 9. AC Measurement I/O Waveform

Figure 10. AC Measurement Load Circuit

Table 10. Device Capacitance

Note: Sampled only, not 100% tested.

Parameter

M29W160E

Unit

Min

Max

Min

Max

Supply Voltage

2.7

3.6

2.7

3.6

Ambient Operating Temperature

°C

Load Capacitance (C

)

Input Rise and Fall Times

Input Pulse Voltages

0 to V

Input and Output Timing Ref. Voltages

AI04498

VCC

VCC/2

AI04499

CL includes JIG capacitance

DEVICE

UNDER

TEST

25k

VCC

25k

VCC

0.1µF

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

M29W160ET, M29W160EB

22/40

Figure 11. Read Mode AC Waveforms

Table 12. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

Test Condition

M29W160E

Unit

AVAV

Address Valid to Next Address Valid

E = V

G = V

Min

AVQV

ACC

Address Valid to Output Valid

E = V

G = V

Max

ELQX

(1)

Chip Enable Low to Output Transition

G = V

Min

ELQV

Chip Enable Low to Output Valid

G = V

Max

GLQX

(1)

OLZ

Output Enable Low to Output Transition

E = V

Min

GLQV

Output Enable Low to Output Valid

E = V

Max

EHQZ

(1)

Chip Enable High to Output Hi-Z

G = V

Max

GHQZ

(1)

Output Enable High to Output Hi-Z

E = V

Max

EHQX

GHQX

AXQX

Chip Enable, Output Enable or Address
Transition to Output Transition

Min

ELBL

ELBH

ELFL

ELFH

Chip Enable to BYTE Low or High

Max

BLQZ

FLQZ

BYTE Low to Output Hi-Z

Max

BHQV

FHQV

BYTE High to Output Valid

Max

AI02922

tAVAV

tAVQV

tAXQX

tELQX

tEHQZ

tGLQV

tGLQX

tGHQX

VALID

A0-A19/
A1

DQ0-DQ7/
DQ8-DQ15

tELQV

tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH

tBLQZ

BYTE

23/40

M29W160ET, M29W160EB

Figure 12. Write AC Waveforms, Write Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

M29W160E

Unit

AVAV

Address Valid to Next Address Valid

Min

ELWL

Chip Enable Low to Write Enable Low

Min

WLWH

Write Enable Low to Write Enable High

Min

DVWH

Input Valid to Write Enable High

Min

WHDX

Write Enable High to Input Transition

Min

WHEH

Write Enable High to Chip Enable High

Min

WHWL

WPH

Write Enable High to Write Enable Low

Min

AVWL

Address Valid to Write Enable Low

Min

WLAX

Write Enable Low to Address Transition

Min

GHWL

Output Enable High to Write Enable Low

Min

WHGL

OEH

Write Enable High to Output Enable Low

Min

WHRL

(1)

BUSY

Program/Erase Valid to RB Low

Max

VCHEL

VCS

High to Chip Enable Low

Min

µs

AI02923

A0-A19/
A1

DQ0-DQ7/
DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWH

tGHWL

tWHRL

M29W160ET, M29W160EB

24/40

Figure 13. Write AC Waveforms, Chip Enable Controlled

Table 14. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol

Alt

Parameter

M29W160E

Unit

AVAV

Address Valid to Next Address Valid

Min

WLEL

Write Enable Low to Chip Enable Low

Min

ELEH

Chip Enable Low to Chip Enable High

Min

DVEH

Input Valid to Chip Enable High

Min

EHDX

Chip Enable High to Input Transition

Min

EHWH

Chip Enable High to Write Enable High

Min

EHEL

CPH

Chip Enable High to Chip Enable Low

Min

AVEL

Address Valid to Chip Enable Low

Min

ELAX

Chip Enable Low to Address Transition

Min

GHEL

Output Enable High Chip Enable Low

Min

EHGL

OEH

Chip Enable High to Output Enable Low

Min

EHRL

(1)

BUSY

Program/Erase Valid to RB Low

Max

VCHWL

VCS

High to Write Enable Low

Min

µs

AI02924

A0-A19/
A1

DQ0-DQ7/
DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEH

tGHEL

tEHRL

29/40

M29W160ET, M29W160EB

APPENDIX A. BLOCK ADDRESS TABLE

Table 19. Top Boot Block Addresses,
M29W160ET

Table 20. Bottom Boot Block Addresses,
M29W160EB

Size

(KBytes)

Address Range

(x8)

Address Range

(x16)

1FC000h-1FFFFFh

FE000h-FFFFFh

1FA000h-1FBFFFh

FD000h-FDFFFh

1F8000h-1F9FFFh

FC000h-FCFFFh

1F0000h-1F7FFFh

F8000h-FBFFFh

1E0000h-1EFFFFh

F0000h-F7FFFh

1D0000h-1DFFFFh

E8000h-EFFFFh

1C0000h-1CFFFFh

E0000h-E7FFFh

1B0000h-1BFFFFh

D8000h-DFFFFh

1A0000h-1AFFFFh

D0000h-D7FFFh

190000h-19FFFFh

C8000h-CFFFFh

180000h-18FFFFh

C0000h-C7FFFh

170000h-17FFFFh

B8000h-BFFFFh

160000h-16FFFFh

B0000h-B7FFFh

150000h-15FFFFh

A8000h-AFFFFh

140000h-14FFFFh

A0000h-A7FFFh

130000h-13FFFFh

98000h-9FFFFh

120000h-12FFFFh

90000h-97FFFh

110000h-11FFFFh

88000h-8FFFFh

100000h-10FFFFh

80000h-87FFFh

0F0000h-0FFFFFh

78000h-7FFFFh

0E0000h-0EFFFFh

70000h-77FFFh

0D0000h-0DFFFFh

68000h-6FFFFh

0C0000h-0CFFFFh

60000h-67FFFh

0B0000h-0BFFFFh

58000h-5FFFFh

0A0000h-0AFFFFh

50000h-57FFFh

090000h-09FFFFh

48000h-4FFFFh

080000h-08FFFFh

40000h-47FFFh

070000h-07FFFFh

38000h-3FFFFh

060000h-06FFFFh

30000h-37FFFh

050000h-05FFFFh

28000h-2FFFFh

040000h-04FFFFh

20000h-27FFFh

030000h-03FFFFh

18000h-1FFFFh

020000h-02FFFFh

10000h-17FFFh

010000h-01FFFFh

08000h-0FFFFh

000000h-00FFFFh

00000h-07FFFh

Size

(KBytes)

Address Range

(x8)

Address Range

(x16)

1F0000h-1FFFFFh

F8000h-FFFFFh

1E0000h-1EFFFFh

F0000h-F7FFFh

1D0000h-1DFFFFh

E8000h-EFFFFh

1C0000h-1CFFFFh

E0000h-E7FFFh

1B0000h-1BFFFFh

D8000h-DFFFFh

1A0000h-1AFFFFh

D0000h-D7FFFh

190000h-19FFFFh

C8000h-CFFFFh

180000h-18FFFFh

C0000h-C7FFFh

170000h-17FFFFh

B8000h-BFFFFh

160000h-16FFFFh

B0000h-B7FFFh

150000h-15FFFFh

A8000h-AFFFFh

140000h-14FFFFh

A0000h-A7FFFh

130000h-13FFFFh

98000h-9FFFFh

120000h-12FFFFh

90000h-97FFFh

110000h-11FFFFh

88000h-8FFFFh

100000h-10FFFFh

80000h-87FFFh

0F0000h-0FFFFFh

78000h-7FFFFh

0E0000h-0EFFFFh

70000h-77FFFh

0D0000h-0DFFFFh

68000h-6FFFFh

0C0000h-0CFFFFh

60000h-67FFFh

0B0000h-0BFFFFh

58000h-5FFFFh

0A0000h-0AFFFFh

50000h-57FFFh

090000h-09FFFFh

48000h-4FFFFh

080000h-08FFFFh

40000h-47FFFh

070000h-07FFFFh

38000h-3FFFFh

060000h-06FFFFh

30000h-37FFFh

050000h-05FFFFh

28000h-2FFFFh

040000h-04FFFFh

20000h-27FFFh

030000h-03FFFFh

18000h-1FFFFh

020000h-02FFFFh

10000h-17FFFh

010000h-01FFFFh

08000h-0FFFFh

008000h-00FFFFh

04000h-07FFFh

006000h-007FFFh

03000h-03FFFh

004000h-005FFFh

02000h-02FFFh

000000h-003FFFh

00000h-01FFFh

M29W160ET, M29W160EB

30/40

APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Tables 21, 22, 23, 24, 25

and 26 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 26, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
Note: The Common Flash Interface is only avail-
able for Temperature range 6 (40 to 85°C).

Table 21. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 22. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.

Address

Sub-section Name

Description

x16

10h

20h

CFI Query Identification String

Command set ID and algorithm data offset

1Bh

36h

System Interface Information

Device timing & voltage information

27h

4Eh

Device Geometry Definition

Flash device layout

40h

80h

Primary Algorithm-specific Extended
Query table

Additional information specific to the Primary
Algorithm (optional)

61h

C2h

Security Code Area

64 bit unique device number

Address

Data

Description

Value

x16

10h

20h

0051h

"Q"

11h

22h

0052h

Query Unique ASCII String "QRY"

"R"

12h

24h

0059h

"Y"

13h

26h

0002h

Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm

AMD

Compatible

14h

28h

0000h

15h

2Ah

0040h

Address for Primary Algorithm extended Query table (see Table 24)

P = 40h

16h

2Ch

0000h

17h

2Eh

0000h

Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported

18h

30h

0000h

19h

32h

0000h

Address for Alternate Algorithm extended Query table

1Ah

34h

0000h

31/40

M29W160ET, M29W160EB

Table 23. CFI Query System Interface Information

Address

Data

Description

Value

x16

1Bh

36h

0027h

Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

2.7V

1Ch

38h

0036h

Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

3.6V

1Dh

3Ah

0000h

[Programming] Supply Minimum Program/Erase voltage

1Eh

3Ch

0000h

[Programming] Supply Maximum Program/Erase voltage

1Fh

3Eh

0004h

Typical timeout per single Byte/Word program = 2

µs

16µs

20h

40h

0000h

Typical timeout for minimum size write buffer program = 2

µs

21h

42h

000Ah

Typical timeout per individual block erase = 2

22h

44h

0000h

Typical timeout for full chip erase = 2

23h

46h

0004h

Maximum timeout for Byte/Word program = 2

times typical

256µs

24h

48h

0000h

Maximum timeout for write buffer program = 2

times typical

25h

4Ah

0003h

Maximum timeout per individual block erase = 2

times typical

26h

4Ch

0000h

Maximum timeout for chip erase = 2

times typical

M29W160ET, M29W160EB

32/40

Table 24. Device Geometry Definition

Address

Data

Description

Value

x16

27h

4Eh

0015h

Device Size = 2

in number of Bytes

2 MByte

28h
29h

50h
52h

0002h
0000h

Flash Device Interface Code description

x8, x16

Async.

2Ah
2Bh

54h
56h

0000h
0000h

Maximum number of Bytes in multi-Byte program or page = 2

2Ch

58h

0004h

Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.

2Dh
2Eh

5Ah
5Ch

0000h
0000h

Region 1 Information
Number of identical size erase block = 0000h+1

2Fh
30h

5Eh

60h

0040h
0000h

Region 1 Information
Block size in Region 1 = 0040h * 256 Byte

16 KByte

31h
32h

62h
64h

0001h
0000h

Region 2 Information
Number of identical size erase block = 0001h+1

33h
34h

66h
68h

0020h
0000h

Region 2 Information
Block size in Region 2 = 0020h * 256 Byte

8 KByte

35h
36h

6Ah
6Ch

0000h
0000h

Region 3 Information
Number of identical size erase block = 0000h+1

37h
38h

6Eh

70h

0080h
0000h

Region 3 Information
Block size in Region 3 = 0080h * 256 Byte

32 KByte

39h

3Ah

72h
74h

001Eh

0000h

Region 4 Information
Number of identical-size erase block = 001Eh+1

3Bh
3Ch

76h
78h

0000h
0001h

Region 4 Information
Block size in Region 4 = 0100h * 256 Byte

64 KByte

33/40

M29W160ET, M29W160EB

Table 25. Primary Algorithm-Specific Extended Query Table

Table 26. Security Code Area

Address

Data

Description

Value

x16

40h

80h

0050h

Primary Algorithm extended Query table unique ASCII string "PRI"

"P"

41h

82h

0052h

"R"

42h

84h

0049h

"I"

43h

86h

0031h

Major version number, ASCII

"1"

44h

88h

0030h

Minor version number, ASCII

"0"

45h

8Ah

0000h

Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

Yes

46h

8Ch

0002h

Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write

47h

8Eh

0001h

Block Protection
00 = not supported, x = number of blocks in per group

48h

90h

0001h

Temporary Block Unprotect
00 = not supported, 01 = supported

Yes

49h

92h

0004h

Block Protect /Unprotect
04 = M29W400B

4Ah

94h

0000h

Simultaneous Operations, 00 = not supported

4Bh

96h

0000h

Burst Mode, 00 = not supported, 01 = supported

4Ch

98h

0000h

Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page Word

Address

Data

Description

x16

61h

C3h, C2h

XXXX

64 bit: unique device number

62h

C5h, C4h

XXXX

63h

C7h, C6h

XXXX

64h

C9h, C8h

XXXX

M29W160ET, M29W160EB

34/40

APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash
memory. Each Block can be protected individually.
Once protected, Program and Erase operations
on the block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks could change between differ-
ent Flash memory suppliers.
Programmer Technique
The Programmer technique uses high (V

) volt-

age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 17,
Programmer Equipment Block Protect Flowchart.
During the Block Protect algorithm, the A19-A12
Address Inputs indicate the address of the block to
be protected. The block will be correctly protected
only if A19-A12 remain valid and stable, and if
Chip Enable is kept Low, V

, all along the Protect

and Verify phases.
The Chip Unprotect algorithm is used to unprotect
all the memory blocks at the same time. This algo-
rithm can only be used if all of the blocks are pro-
tected first. To unprotect the chip follow Figure 18,

Programmer Equipment Chip Unprotect Flow-
chart. Table 27, Programmer Technique Bus Op-
erations, gives a summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash memory has been fitted to
the system.
To protect a block follow the flowchart in Figure 19,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig-
ure 20, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.

Table 27. Programmer Technique Bus Operations, BYTE = V

or V

Operation

Address Inputs

A0-A19

Data Inputs/Outputs

DQ15A1, DQ14-DQ0

Block Protect

Pulse

A9 = V

, A12-A19 Block Address

Others = X

Chip Unprotect

Pulse

A9 = V

, A12 = V

, A15 = V

Others = X

Block Protection
Verify

A0 = V

, A1 = V

, A6 = V

, A9 = V

A12-A19 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection
Verify

A0 = V

, A1 = V

, A6 = V

, A9 = V

A12-A19 Block Address

Others = X

Retry = XX01h

Pass = XX00h

M29W160ET, M29W160EB

40/40

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information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support

devices or systems without express written approval of STMicroelectronics.

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