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PRELIMINARY DATA

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29W200BT

M29W200BB

2 Mbit (256Kb x8 or 128Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 55ns

PROGRAMMING TIME

s per Byte/Word typical

7 MEMORY BLOCKS

1 Boot Block (Top or Bottom Location)

2 Parameter and 4 Main Blocks

PROGRAM/ERASE CONTROLLER

Embedded Byte/Word Program algorithm

Embedded Multi-Block/Chip Erase algorithm

Status Register Polling and Toggle Bits

Ready/Busy Output Pin

ERASE SUSPEND and RESUME MODES

Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

Faster Production/Batch Programming

TEMPORARY BLOCK UNPROTECTION
MODE

LOW POWER CONSUMPTION

Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per
BLOCK

20 YEARS DATA RETENTION

Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

Manufacturer Code: 0020h

Top Device Code M29W200BT: 0051h

Bottom Device Code: M29W200BB 0057h

TSOP48 (N)

12 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI02948

A0-A16

DQ0-DQ14

VCC

M29W200BT

M29W200BB

VSS

DQ15A1

BYTE

M29W200BT, M29W200BB

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Figure 2. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A10

DQ14

DQ12

DQ10

DQ15A1

VCC

DQ4

DQ5

DQ7

AI02944

M29W200BT
M29W200BB

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14

VSS

Figure 3. SO Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A1

DQ5

DQ2

DQ3

VCC

DQ11

DQ4

DQ14

AI02945

M29W200BT

M29W200BB

DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10

DQ12

Table 1. Signal Names

A0-A16

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

Data Inputs/Outputs

DQ15A1

Data Input/Output or Address Input

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

BYTE

Byte/Word Organization Select

Supply Voltage

Ground

Not Connected Internally

SUMMARY DESCRIPTION
The M29W200B is a 2 Mbit (256Kb x8 or 128Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM. The M29W200B is fully
backward compatible with the M29W200.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

3/22

M29W200BT, M29W200BB

The blocks in the memory are asymmetrically ar-
ranged, see Tables 3 and 4, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro-
processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.

Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to '1').

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

Ambient Operating Temperature (Temperature Range Option 6)

40 to 85

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage

0.6 to 4

Supply Voltage

0.6 to 4

Identification Voltage

0.6 to 13.5

Table 3. Top Boot Block Addresses
M29W200BT

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

3C000h-3FFFFh

1E000h-1FFFFh

3A000h-3BFFFh

1D000h-1DFFFh

38000h-39FFFh

1C000h-1CFFFh

30000h-37FFFh

18000h-1BFFF h

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFFh

00000h-0FFFFh

00000h-07FFFh

Table 4. Bottom Boot Block Addresses
M29W200BB

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

30000h-3FFFFh

18000h-1FFFF h

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFF h

08000h-0FFFFh

04000h-07FFFh

06000h-07FFFh

03000h-03FFFh

04000h-05FFFh

02000h-02FFFh

00000h-03FFFh

00000h-01FFFh

M29W200BT, M29W200BB

4/22

SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A16). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V

. When BYTE is Low, V

, these pins

are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V

, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V

, this pin behaves as an address

pin; DQ15A1 Low will select the LSB of the Word
on the other addresses, DQ15A1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory's Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all Blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

RHEL

, whichever occurs last. See the Ready/Busy

Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V

will temporarily unprotect the

protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V

. Ready/Busy will remain Low during

Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
V

, the memory is in 8-bit mode, when it is High,

, the memory is in 16-bit mode.

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,
V

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1

F capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

CC3

Ground. The V

Ground is the reference for

all voltage measurements.

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M29W200BT, M29W200BB

Table 5. Bus Operations, BYTE = V

Note: X = V

or V

Table 6. Bus Operations, BYTE = V

Note: X = V

or V

Operation

Address Inputs

DQ15A1, A0-A16

Data Inpu ts/Outputs

DQ14-DQ8

DQ7-DQ0

Bus Read

Cell Address

Hi-Z

Data Output

Bus Write

Command Address

Hi-Z

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

20h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

51h (M29W200BT)

57h (M29W200BB)

Operation

Address Inputs

A0-A16

Data Inpu ts/Outputs

DQ15A1, DQ14-DQ0

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer
Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

0020h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

0051h (M29W200BT)

0057h (M29W200BB)

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I

CC2

, Chip Enable should

be held within V

0.2V. For the Standby current

level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC3

, for Program or Erase operations un-

til the operation completes.

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