1/33

March 2000

M29W800AT

M29W800AB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory

2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 80ns

PROGRAMMING TIME: 10

s typical

PROGRAM/ERASE CONTROLLER (P/E.C.)

Program Byte-by-Byte or Word-by-Word

Status Register bits and Ready/Busy Output

SECURITY PROTECTION MEMORY AREA

INSTRUCTION ADDRESS CODING: 3 digits

MEMORY BLOCKS

Boot Block (Top or Bottom location)

Parameter and Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES

ERASE SUSPEND and RESUME MODES

Read and Program another Block during

Erase Suspend

LOW POWER CONSUMPTION

Stand-by and Automatic Stand-by

100,000 PROGRAM/ERASE CYCLES per
BLOCK

20 YEARS DATA RETENTION

Defectivity below 1ppm/year

ELECTRONIC SIGNATURE

Manufacturer Code: 20h

Top Device Code, M29W800AT: D7h

Bottom Device Code, M29W800AB: 5Bh

Figure 1. Logic Diagram

AI02599

A0-A18

DQ0-DQ14

VCC

M29W800AT

M29W800AB

VSS

DQ15A1

BYTE

FBGA

TSOP48 (N)

12 x 20mm

SO44 (M)

LFBGA48 (ZA)

8 x 6 solder balls

M29W800AT, M29W800AB

2/33

Figure 2. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A17

A10

DQ14

DQ12

DQ10

DQ15A1

VCC

DQ4

DQ5

DQ7

AI02179

M29W800T

M29W800B

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14

VSS

Figure 3. SO Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A1

DQ5

DQ2

DQ3

VCC

DQ11

DQ4

DQ14

AI02181

M29W800T

M29W800B

DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10

DQ12

A17

A18

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ7

Data Input/Outputs, Command Inputs

DQ8-DQ14

Data Input/Outputs

DQ15A1

Data Input/Output or Address Input

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

BYTE

Byte/Word Organization

Supply Voltage

Ground

Not Connected Internally

Don't Use as Internally Connected

DESCRIPTION
The M29W800A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or
Word-by-Word basis using only a single 2.7V to
3.6V V

supply. For Program and Erase opera-

tions the necessary high voltages are generated
internally. The device can also be programmed in
standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the de-
vice in cycles of commands to a Command Inter-
face using standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm),
SO44 and LFBGA48 0.8 mm ball pitch packages.

3/33

M29W800AT, M29W800AB

Figure 4. LFBGA Connections (Top view through package)

AI00656

VSS

DQ15

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

DQ1

DQ9

DQ8

DQ0

A17

DQ2

DQ6

DQ13

DQ14

A10

DQ4

VCC

DQ12

DQ5

A11

DQ7

VSS

A16

BYTE

Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800AT and M29W800AB devices have an
array of 19 blocks, one Boot Block of 16 KBytes or
8 KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteen Main Blocks of 64 KBytes or
32 KWords. The M29W800AT has the Boot Block
at the top of the memory address space and the
M29W800AB locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
5.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the P/
E.C. The block erase operation can be suspended
in order to read from or program to any block not
being erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.

Organisation
The M29W800A is organised as 1M x8 or 512K
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is se-
lected and the address lines are DQ15A1 and
A0-A18. The Data Input/Output signal DQ15A1
acts as address line A1 which selects the lower
or upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A18 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-lev-
el input provides a hardware reset when pulled
Low, and when held High (at V

) temporarily un-

protects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.

M29W800AT, M29W800AB

4/33

Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature, Block Protection Status), Write com-
mand, Output Disable, Stan-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro-
tection Verify and Block Temporary Unprotection.
See Tables 5 and 6.
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Com-
mand' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume.

The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase op-
erations. The Status Register Data Polling,
Toggle, Error bits and the RB output may be read
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 9).
The third cycle inputs the instruction set-up com-
mand. Subsequent cycles output the addressed
data, Electronic Signature or Block Protection Sta-
tus for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command in-
puts. For a Program instruction, the fourth com-
mand cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm com-
mand on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed. When power is first ap-
plied or if V

falls below V

LKO

, the command in-

terface is reset to Read Array.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.
3. Depends on range.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

40 to 85

BIAS

Temperature Under Bias

50 to 125

STG

Storage Temperature

65 to 150

(2)

Input or Output Voltage

0.6 to 5

Supply Voltage

0.6 to 5

(A9, E, G, RP)

(2)

A9, E, G, RP Voltage

0.6 to 13.5

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M29W800AT, M29W800AB

Table 3. Top Boot Block Addresses,
M29W800AT

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

FC000h-FFFFFh

7E000h-7FFFFh

FA000h-FBFFFh

7D000h-7DFFFh

F8000h-F9FFFh

7C000h-7CFFFh

F0000h-F7FFFh

78000h-7BFFFh

E0000h-EFFFFh

70000h-77FFFh

D0000h-DFFFFh

68000h-6FFFFh

C0000h-CFFFFh

60000h-67FFFh

B0000h-BFFFFh

58000h-5FFFFh

A0000h-AFFFFh

50000h-57FFFh

90000h-9FFFFh

48000h-4FFFFh

80000h-8FFFFh

40000h-47FFFh

70000h-7FFFFh

38000h-3FFFFh

60000h-6FFFFh

30000h-37FFFh

50000h-5FFFFh

28000h-2FFFFh

40000h-4FFFFh

20000h-27FFFh

30000h-3FFFFh

18000h-1FFFFh

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFFh

00000h-0FFFFh

00000h-07FFFh

Table 4. Bottom Boot Block Addresses,
M29W800AB

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

F0000h-FFFFFh

78000h-7FFFFh

E0000h-EFFFFh

70000h-77FFFh

D0000h-DFFFFh

68000h-6FFFFh

C0000h-CFFFFh

60000h-67FFFh

B0000h-BFFFFh

58000h-5FFFFh

A0000h-AFFFFh

50000h-57FFFh

90000h-9FFFFh

48000h-4FFFFh

80000h-8FFFFh

40000h-47FFFh

70000h-7FFFFh

38000h-3FFFFh

60000h-6FFFFh

30000h-37FFFh

50000h-5FFFFh

28000h-2FFFFh

40000h-4FFFFh

20000h-27FFFh

30000h-3FFFFh

18000h-1FFFFh

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFFh

04000h-07FFFh

06000h-07FFFh

03000h-03FFFh

04000h-05FFFh

02000h-02FFFh

00000h-03FFFh

00000h-01FFFh

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