AI02178
19
A0-A18
W
DQ0-DQ14
VCC
M29W800T
M29W800B
E
VSS
15
G
RP
DQ15A1
BYTE
RB
Figure 1. Logic Diagram
M29W800T
M29W800B
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W800T and M29W800B are replaced
respectively by the M29W800AT and
M29W800AB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 90ns
FAST PROGRAMMING TIME
10
s by Byte / 20
s by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
Program Byte-by-Byte or Word-by-Word
Status Register bits and Ready/Busy Output
MEMORY BLOCKS
Boot Block (Top or Bottom location)
Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Device Code, M29W800T: 00D7h
Device Code, M29W800B: 005Bh
DESCRIPTION
The M29W800 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byteor Word-
by-Word basis using only a single 2.7V to 3.6V V
CC
supply. For Program and Erase operations the
necessary high voltages are generated internally.
The device can also be programmed in standard
programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
June 1999
1/33
This is information on a product still in production but not recommended for new designs.
44
1
SO44 (M)
TSOP48 (N)
12 x 20 mm
DQ3
DQ9
DQ2
A6
DQ0
W
A3
RB
DQ6
A8
A9
DQ13
A17
A10
DQ14
A2
DQ12
DQ10
DQ15A1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI02179
M29W800T
M29W800B
(Normal)
12
1
13
24
25
36
37
48
DQ8
NC
NC
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14
VSS
E
A0
RP
VSS
Figure 2A. TSOP Pin Connections
G
DQ0
DQ8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
DQ7
A12
A16
BYTE
DQ15A1
DQ5
DQ2
DQ3
VCC
DQ11
DQ4
DQ14
A9
W
RB
A4
RP
A7
AI02181
M29W800T
M29W800B
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
DQ1
DQ9
A6
A5
DQ6
DQ13
44
39
38
37
36
35
34
33
A11
A10
DQ10
21
DQ12
40
43
1
42
41
A17
A8
A18
Figure 2C. SO Pin Connections
DQ3
DQ9
DQ2
DQ0
DQ6
DQ13
DQ14
DQ12
DQ10
DQ15A1
VCC
DQ4
DQ5
DQ7
AI02180
M29W800T
M29W800B
(Reverse)
12
1
13
24
25
36
37
48
DQ8
DQ1
DQ11
A16
BYTE
VSS
A0
VSS
A6
A3
A8
A9
A17
A10
A2
A7
NC
NC
NC
NC
A1
A18
A4
A5
A12
A13
A11
A15
A14
RP
W
RB
G
E
Figure 2B. TSOP Reverse Pin Connections
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Outputs, Command Inputs
DQ8-DQ14
Data Input/Outputs
DQ15A1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset / Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organisation
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
Warning: NC = Not Connected.
Warning: NC = Not Connected.
2/33
M29W800T, M29W800B
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commandsto a Command Interfaceusing
standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm) and
SO44 packages. Both normal and reverse pinouts
are available for the TSOP48 package.
Organisation
The M29W800 is organised as 1 M x8 or 512K x16
bits selectable by the BYTE signal. When BYTE is
Low the Byte-wide x8 organisation is selected and
the address lines are DQ15A1 and A0-A18. The
Data Input/Output signal DQ15A1 acts as ad-
dress line A1 which selects the lower or upper
Byte of the memory word for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedan ce. When
BYTE is High the memory uses the address inputs
A0-A18 and the Data Input/Outputs DQ0-DQ15.
Memory control is provided by Chip Enable E,
Output Enable G and Write Enable W inputs.
AReset/Block TemporaryUnprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
ID
) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
DESCRIPTION (Cont'd)
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800Tand M29W800Bdevices have an array
of 19 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteenMain Blocks of 64 KBytes or 32
KWords. The M29W800T has the Boot Block at the
top of the memory address space and the
M29W800B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t ec t i o n , U np r o t e ct i o n, P ro t e cti on Ver i f y,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 85
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
(2)
Input or Output Voltages
0.6 to 5
V
V
CC
Supply Voltage
0.6 to 5
V
V
(A9, E, G, RP)
(2)
A9, E, G, RP Voltage
0.6 to 13.5
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns.
3. Depends on range.
Table 2. Absolute Maximum Ratings
(1)
3/33
M29W800T, M29W800B
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