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PRELIMINARY DATA
August 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M34C00
3 x 128 bit Serial IC Bus EEPROM
For ee-Tags
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
8
1
Figure 1. Logic Diagram
AI03394
SDA
VCC
M34C00
SCL
VSS
Table 1. Signal Names
SDA
Serial Data
SCL
Serial Clock
V
CC
Supply Voltage
V
SS
Ground
s
Two-Wire I
2
C Serial Interface
Supports 400 kHz Protocol
s
2.5 V to 5.5 V Single Supply Voltage
s
384-bit EEPROM divided in three areas:
128 bits of non-erasable memory
128 bits of standard EEPROM
128 bits that can be permanently Write-
protected (to behave as ROM)
s
Self-Timed Program Cycle
s
Enhanced ESD/Latch-Up Protection
s
More than 1 Million Erase/Write Cycles
s
More than 40 Year Data Retention
DESCRIPTION
The M34C00 is a 384-bit serial EEPROM. The
bottom third of the memory area (from location 00h
to 0Fh) can be Write-protected using a specially
designed software Write-protection mechanism.
By sending the device a specific sequence, the
first 128 bits of the memory become permanently
Write-protected. Care must be taken when using
this sequence as its effect cannot be reversed.
The top third of the memory area (from location
20h to 2Fh) is already configured to give the
functional equivalence of a non-erasable memory.
That is, it is initialized to all 1s (FFh), and the user
is able to reset any number of those 1s to 0; but
there is no mechanism for the user to set a 0 back
to a 1.
The M34C00 is a 384-bit electrically erasable
programmable memory (EEPROM), organized as
48 x 8 bits.
M34C00
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Figure 2A. SO and TSSOP Connections
Note: 1. NC = Not Connected
1
AI03395B
2
3
4
8
7
6
5
SDA
VSS
SCL
NC
NC
NC
VCC
NC
M34C00
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This signal is used to strobe all data in and out of
the device. In applications where this line is used
by slave devices to synchronize the bus to a
slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
can be calculated). In most applications, though,
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR'ed with other open drain or open
These devices are compatible with the I
2
C
memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The device carries a built-in 4-bit
Device Type Identifier code (1010) in accordance
with the I
2
C bus definition to access the memory
area and a second Device Type Identifier code
(0110) to access the Protection Register.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select code and RW bit (as described in Table 3),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master's 8-bit transmission.
Table 2. Absolute Maximum Ratings
1
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
, R2=500
)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 85
C
T
STG
Storage Temperature
65 to 150
C
T
LEAD
Lead Temperature during Soldering
SOT23: t.b.d.
SO: 20 seconds (max)
2
TSSOP: 20 seconds (max)
2
t.b.d.
235
235
C
V
IO
Input or Output range
0.6 to 6.5
V
V
CC
Supply Voltage
0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
3
4000
V
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M34C00
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
Maximum RP value (k
)
10
1000
fc = 400kHz
fc = 100kHz
Table 3. Device Select Code
Note: 1. The most significant bit (b7) is sent first.
Device Type Identifier
1
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (three arrays)
1
0
1
0
1
1
1
RW
Protection Register Select Code
0
1
1
0
1
1
1
RW
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
.
(Figure 3 indicates how the value of the pull-up
resistor can be calculated).
DEVICE OPERATION
The device supports the I
2
C protocol. This is
summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M34C00
device is always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a programming cycle)
Serial Data (SDA) and Serial Clock (SCL) for a
Start condition, and will not respond unless one is
given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable, and
driven High. A Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9
th
clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the data on Serial Data (SDA)
M34C00
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Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1
2
3
7
8
9
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
MSB
ACK
STOP
Condition
must change
only
when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the 8-bit byte, shown in Table 3, on Serial
Data (SDA) (most significant bit first). This
consists of the 7-bit Device Select code, and the
Read/Write bit (RW).
To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b, as shown in Table 3.
The 8
th
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations. If a
match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Memory Partitioning
The memory is divided in three arrays:
s
Array-0: Write-protectable Array (00h to 0Fh)
s
Array-1: EEPROM Array (10h to 1Fh)
s
Array-2: Non-Erasable Memory Array (20h to
2Fh)
The 4 least significant bits of the address byte
determine the byte that is to be addressed within
the given array. The next 2 more significant
address bits determine the array that is to be
addressed (Array-0, Array-1, Array-2 or Invalid).
The 2 most significant address bits are Don't Care.
If the address is of the form xx11xxxx, the device
recognises that an attempt is being made to
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M34C00
Figure 5. Memory Partitioning
Default EEPROM memory area
state before write access
to the Protection Register
AI03396
Standard
Array
1Fh
Standard
Array
10h
0Fh
00h
Standard
Array
1Fh
Write
Protected
Array
10h
0Fh
00h
State of the EEPROM memory
area after write access
to the Protection Register
2Fh
20h
2Fh
20h
EPROM
Array
EPROM
Array
Array 2
Array 1
Array 0
Array 2
Array 1
Array 0
address the Invalid array, and immediately
deselects itself.
The Write-protectable array consists of 16 bytes of
EEPROM, which can be used as normal EEPROM
until this array is set in its Write-protected mode.
Once Write-protected, this array becomes
functionally equivalent to a Read-Only Memory
(ROM), and cannot be modified further. The
procedure to set this array in its Write-protected
mode is described later.
Array-2 also consists of 16 bytes of EEPROM, but
configured to give the functional equivalence of
non-erasable memory. That is, it is initialized to
contain all 1s (FFh), with the user able to reset any
1 to a 0, but unable to set any 0 to a 1. One
application envisaged for this array is as a non-
resettable 128-token array.
WRITE AND READ OPERATIONS
Write Operations
Following a Start condition the bus master sends
a Device Select code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
6, and waits for an address byte. The device
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the
addressed location is in the Write-protected area,
the device replies with NoAck, and the location is
not modified. If, instead, the addressed location is
not in a Write-protected area, the device replies
with Ack. The bus master terminates the transfer
by generating a Stop condition, as shown in Figure
6.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum Write time (t
w
) is shown in Table 6,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the bus
master.
The sequence, as shown in Figure 7, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select code (the first byte
of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
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