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July 2003

M34C02

2 Kbit Serial I²C Bus EEPROM

For DIMM Serial Presence Detect

FEATURES SUMMARY

Software Data Protection for lower 128 bytes

Two Wire I

C Serial Interface

100kHz and 400kHz Transfer Rates

Single Supply Voltage:

2.5 to 5.5V up to 400kHz for M34C02-W

2.2 to 5.5V up to 400kHz for M34C02-L

1.8 to 5.5V up to 100kHz for M34C02-R

1.7 to 3.6V up to 100kHz for M34C02-F

BYTE and PAGE WRITE (up to 16 bytes)

RANDOM and SEQUENTIAL READ Modes

Self-Timed Programming Cycle

Automatic Address Incrementing

Enhanced ESD/Latch-Up Protection

More than 1 Million Erase/Write Cycles

More than 40 Year Data Retention

Figure 1. Packages

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm² body size (MSOP)

VFDFPN8 (MM)

2x3mm² (MLP)

M34C02

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SUMMARY DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
the memory become permanently write protected.
Care must be taken when using this sequence as
its effect cannot be reversed. In addition, the
device allows the entire memory area to be write
protected, using the WC input (for example by
tieing this input to V

These I

C-compatible electrically erasable

programmable memory (EEPROM) devices are
organized as 256x8 bits.

Figure 2. Logic Diagram

C uses a two wire serial interface, comprising a

bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I

C bus definition to

access the memory area and a second Device
Type Identifier Code (0110) to access the
Protection Register. These codes are used
together with three chip enable inputs (E2, E1, E0)
so that up to eight 2 Kbit devices may be attached
to the I²C bus and selected individually.
The device behaves as a slave device in the I

protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a

Device Select Code and RW bit (as described in
Table 2), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9

bit time,

following the bus master's 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.

Figure 3. DIP, SO, TSSOP and VFDFPN
Connections (Top View)

Note: 1. See the pages after page 19 for package dimensions,

and how to identify pin-1.

Table 1. Signal Names

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
Write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the POR

threshold value, and all operations are disabled
the device will not respond to any command. In the
same way, when V

drops from the operating

voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command.
A stable and valid V

(as defined in Tables 6 to

9) must be applied before applying any logic
signal.

AI01931

E0-E2

SDA

VCC

M34C02

SCL

VSS

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

Write Control

Supply Voltage

Ground

SDA

VSS

SCL

VCC

AI01932C

M34C02

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M34C02

SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to V

. (Figure 4

indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR'ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V

. (Fig-

ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V

or V

to establish the

Device Select Code.
Write Control (WC)

This input signal is provided for protecting the con-
tents of the whole memory from inadvertent write
operations. Write Control (WC) is used to enable
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the Protection Register.
When Write Control (WC) is tied Low or left
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.

Figure 4. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL

CBUS

100

CBUS (pF)

Maximum RP value (k

)

1000

fc = 400kHz

fc = 100kHz

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M34C02

DEVICE OPERATION
The device supports the I

C protocol. This is sum-

marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The memory device is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the
eight data bits.

Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change

only

when Serial Clock (SCL) is driv-

en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable "Address"
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b; to address the
Protection Register, it is 0110b.
Up to eight memory devices can be connected on
a single I

C bus. Each one is given a unique 3-bit

code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the
device only responds if the Chip Enable Address
is the same as the value on the Chip Enable (E0,
E1, E2) inputs.
The 8

bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9

bit time. If the

device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.

Table 3. Operating Modes

Note: 1. X =

or V

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

START, Device Select, RW = 1

Random Address Read

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Sequential Read

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

START, Device Select, RW = 0

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M34C02W

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M34C02W

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M34C02W