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December 1999
M34C02
2 Kbit Serial IC Bus EEPROM
For DIMM Serial Presence Detect
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
8
1
8
1
8
1
s
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
s
Single Supply Voltage:
2.5V to 5.5V for M34C02-W
2.2V to 5.5V for M34C02-L
s
Software Data Protection for lower 128 bytes
s
BYTE and PAGE WRITE (up to 16 bytes)
s
RANDOM and SEQUENTIAL READ Modes
s
Self-Timed Programming Cycle
s
Automatic Address Incrementing
s
Enhanced ESD/Latch-Up Protection
s
1 Million Erase/Write Cycles (minimum)
s
40 Year Data Retention (minimum)
DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
Figure 1. Logic Diagram
AI01931
3
E0-E2
SDA
VCC
M34C02
WC
SCL
VSS
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
M34C02
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the memory become permanently write protected.
Care must be taken when using this sequence as
its effect cannot be reversed. In addition, the
device allows the entire memory area to be write
protected, using the WC input (for example by
tieing this input to V
CC
).
The M34C02 is a 2 Kbit electrically erasable pro-
grammable memory (EEPROM), organized as
256x8 bits, fabricated with STMicroelectronics'
High Endurance, Advanced, CMOS technology.
This guarantees an endurance typically well
above one million Erase/Write cycles, with a data
retention of 40 years. These memory devices
operate with a power supply down to 2.2 V for the
M34C02-L.
The M34C02 is available in Plastic Dual In-line,
Plastic Small Outline and Thin Shrink Small
Outline packages.
These memory devices are compatible with the
I
2
C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
Device Type Identifier code (1010) in accordance
with the I
2
C bus definition to access the memory
area and a second Device Type Identifier Code
(0110) to access the Protection Register. These
codes are used together with three chip enable
inputs (E2, E1, E0) so that up to eight 2 Kbit
devices may be attached to the IC bus and
selected individually.
The memory behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9
th
bit time,
following the bus master's 8-bit transmission.
Figure 2A. DIP Connections
SDA
VSS
SCL
WC
E1
E0
VCC
E2
AI01932
M34C02
1
2
3
4
8
7
6
5
Figure 2B. SO and TSSOP Connections
1
AI01933
2
3
4
8
7
6
5
SDA
VSS
SCL
WC
E1
E0
VCC
E2
M34C02
Table 2. Absolute Maximum Ratings
1
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
-40 to 85
C
T
STG
Storage Temperature
-65 to 150
C
T
LEAD
Lead Temperature during Soldering
PSDIP8: 10 sec
SO8: 40 sec
TSSOP8: 40 sec
260
215
215
C
V
IO
Input or Output range
-0.6 to 6.5
V
V
CC
Supply Voltage
-0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2
4000
V
3/19
M34C02
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V
CC
voltage has reached
the POR threshold value, and all operations are
disabled the device will not respond to any
command. In the same way, when V
CC
drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
valid V
CC
must be applied before applying any
logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to V
CC
. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR'ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to V
CC
. (Figure 3 indicates how the value of
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
V
CC
or V
SS
to establish the device select code.
Write Control (WC)
A hardware Write Control (WC, pin 7) is provided
for protecting the contents of the whole memory
from erroneous erase/write cycles. The Write
Control signal is used to enable (WC=V
IL
) or
disable (WC=V
IH
) write instructions to the entire
memory area or to the Protection Register.
When WC is tied to V
SS
or left unconnected, the
write protection of the first half of the memory is
determined by the status of the Protection
Register.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 4. Any device that
sends data on to the bus is defined to be a
transmitter, and any device that reads the data to
be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
Maximum RP value (k
)
10
1000
fc = 400kHz
fc = 100kHz
M34C02
4/19
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, provided that it is followed by a
NoAck, forces the memory device into its standby
state. A STOP condition at the end of a Write
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Table 3. Device Select Code
1
Note: 1. The most significant bit (b7) is sent first.
Device Type Identifier
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (two arrays)
1
0
1
0
E2
E1
E0
RW
Protection Register Select Code
0
1
1
0
E2
E1
E0
RW
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M34C02
command triggers the internal EEPROM write
cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9
th
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change
only
when
the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable "Address" (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I
2
C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.
The 8
th
bit is the read or write bit (RW). This bit is
set to `1' for read and `0' for write operations. If a
match occurs on the Device Select Code, the
corresponding memory gives an acknowledgment
on the SDA bus during the 9
th
bit time. If the
memory does not match the Device Select code, it
will deselect itself from the bus, and go into stand-
by mode.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to '0', as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address byte, the master sends one
data byte. If the addressed location is in a write
protected area, the memory replies with a NoAck,
and the location is not modified. If, instead, the
addressed location is not in a write protected area,
the memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same 'row' in the memory:
that is the most significant memory address bits
(b7-b4) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as `roll-over' occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 4 least
Table 4. Operating Modes
Note: 1. X =
V
IH
or V
IL
.
Mode
RW bit
WC
1
Bytes
Initial Sequence
Current Address Read
1
X
1
START, Device Select, RW = `1'
Random Address Read
0
X
1
START, Device Select, RW = `0', Address
1
X
reSTART, Device Select, RW = `1'
Sequential Read
1
X
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = `0'
Page Write
0
V
IL
16
START, Device Select, RW = `0'
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