July 2006
Rev. 2
1/23
1
M36P0R9060E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
Feature summary
Multi-Chip Package
1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash memory
1
die of 64 Mbit (4Mb x16)
PSRAM
Supply voltage
V
DDF
= V
CCP
= V
DDQ
= 1.7 to 1.95V
V
PPF
= 9V for fast program
Electronic signature
Manufacturer Code: 20h
Device Code: 8819
ECOPACK package
Flash memory
Synchronous / asynchronous read
Synchronous Burst Read mode:
108MHz, 66MHz
Asynchronous Page Read mode
Random Access: 96ns
Programming time
4.2s typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
Multiple Bank memory array: 64 Mbit banks
Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
program/erase in one Bank while read in
others
No delay between read and write
operations
Security
64 bit unique device number
2112 bit user programmable OTP Cells
100,000 Program/erase cycles per block
Common Flash Interface (CFI)
Block locking
All Blocks locked at power-up
Any combination of Blocks can be locked
with zero latency
WP
F
for Block Lock-Down
Absolute Write Protection with V
PPF
= V
SS
PSRAM
User-selectable operating modes
Asynchronous modes: Random Read, and
Write, Page Read
Synchronous modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
Asynchronous Random Read
Access time: 70ns
Asynchronous Page Read
Page size: 4, 8 or 16 Words
Subsequent Read within Page: 20ns
Burst Read
Fixed length (4, 8, 16 or 32 Words) or
Continuous
Low power consumption
Active current: < 25mA
Standby current: 140A
Deep Power-Down current: < 10A
Low-power features
Partial Array Self-Refresh (PASR)
Deep Power-Down (DPD) Mode
Automatic Temperature-compensated Self-
Refresh
TFBGA107 (ZAC)
FBGA
www.st.com
M36P0R9060E0
2/23
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Flash Chip Enable input (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Flash Output Enable inputs (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Flash Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Flash Write Protect (WP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Flash Reset (RP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11
PSRAM Chip Enable input (E
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
PSRAM Write Enable (W
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
PSRAM Output Enable (G
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
PSRAM Upper Byte Enable (UB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
PSRAM Lower Byte Enable (LB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16
PSRAM Configuration Register Enable (CR
P
) . . . . . . . . . . . . . . . . . . . . . 11
2.17
Deep Power-Down input (DPD
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18
V
DDF
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.19
V
CCP
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.20
V
DDQ
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21
V
PPF
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.22
V
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M36P0R9060E0
3/23
6
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M36P0R9060E0
4/23
List of tables
Table 1.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2.
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4.
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5.
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7.
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M36P0R9060E0
5/23
List of figures
Figure 1.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4.
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5.
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6.
TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . 19
PDF 
ZIP