M95040, M95020, M95010

2/37

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M95040, M95020, M95010

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Address Range Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Operating Conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Operating Conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Operating Conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. DC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. DC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. DC Characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. DC Characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. DC Characteristics (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18. AC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. AC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. AC Characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. AC Characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. AC Characteristics (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19.PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 32

M95040, M95020, M95010

4/37

Table 23. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 32

Figure 20.SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 33

Table 24. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
33

Figure 21.TSSOP8 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 34

Table 25. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 34

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27. How to Identify Present and Previous Products by the Process Identification Letter . . . 35

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

M95040, M95020, M95010

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SIGNAL DESCRIPTION

During all operations, V

must be held stable and

within the specified valid range: V

(min) to

(max).

All of the input and output signals can be held High
or Low (according to voltages of V

, V

, as specified in

Table 13.

Table 17.

). These

signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).

Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). This input signal is used to
control whether the memory is write protected.
When Write Protect (W) is held Low, writes to the
memory are disabled, but other operations remain
enabled. Write Protect (W) must either be driven
High or Low, but must not be left floating.

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M95040, M95020, M95010

CONNECTING TO THE SPI BUS

These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output

(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.

Figure 4.

shows three devices, connected to an

MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.

Figure 4. Bus Master and Memory Devices on the SPI Bus

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

SPI Memory

Device

SPI Memory

Device

CS3

CS2

CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

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M95040, M95020, M95010

OPERATING FEATURES

Power-up
When the power supply is turned on, V

rises

from V

to V

During this time, the Chip Select (S) must be al-
lowed to follow the V

voltage. It must not be al-

lowed to float, but should be connected to V

via

a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V

Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
consumes I

, as specified in

Table 13.

Table

17.

When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby

Power mode, and the device consumption drops
to I

CC1

Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in

Figure

The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.

Figure 6.

also shows what happens if the rising

and falling edges are not timed to coincide with
Serial Clock (C) being Low.

Figure 6. Hold Condition Activation

AI02029D

HOLD

Hold

Condition

Hold

Condition

M95040, M95020, M95010

10/37

Status Register

Figure 7.

shows the position of the Status Register

in the control logic of the device. This register con-
tains a number of control bits and status bits, as
shown in

Table 3.

Bits b7, b6, b5 and b4 are always read as 1.
WIP bit. The Write In Progress bit is a volatile
read-only bit that is automatically set and reset by
the internal logic of the device. When set to a 1, it
indicates that the memory is busy with a Write cy-
cle.
WEL bit. The Write Enable Latch bit is a volatile
read-only bit that is set and reset by specific in-
structions. When reset to 0, no WRITE or WRSR
instructions are accepted by the device.
BP1, BP0 bits. The Block Protect bits are non-
volatile read-write bits. These bits define the area
of memory that is protected against the execution
of Write cycles, as summarized in

Table 4.

Table 3. Status Register Format

Data Protection and Protocol Control
To help protect the device from data corruption in
noisy or poorly controlled environments, a number
of safety features have been built in to the device.
The main security measures can be summarized
as follows:

The WEL bit is reset at power-up.

Chip Select (S) must rise after the eighth clock
count (or multiple thereof) in order to start a
non-volatile Write cycle (in the memory array
or in the Status Register).

Accesses to the memory array are ignored
during the non-volatile programming cycle,
and the programming cycle continues
unaffected.

Invalid Chip Select (S) and Hold (HOLD)
transitions are ignored.

For any instruction to be accepted and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches the last bit of
the instruction, and before the next rising edge of
Serial Clock (C).
For this, "the last bit of the instruction" can be the
eighth bit of the instruction code, or the eighth bit
of a data byte, depending on the instruction (ex-
cept in the case of RDSR and READ instructions).
Moreover, the "next rising edge of CLOCK" might
(or might not) be the next bus transaction for some
other device on the bus.
When a Write cycle is in progress, the device pro-
tects it against external interruption by ignoring
any subsequent READ, WRITE or WRSR instruc-
tion until the present cycle is complete.

Table 4. Write-Protected Block Size

b7 b0

1 BP1 BP0 WEL WIP

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

Status Register Bits

Protected Block

Array Addresses Protected

BP1 BP0

M95040

M95020

M95010

0 0

none

Upper quarter

180h - 1FFh

C0h - FFh

60h - 7Fh

Upper half

100h - 1FFh

80h - FFh

40h - 7Fh

Whole memory

000h - 1FFh

00h - FFh

00h - 7Fh

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M95040, M95020, M95010

Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.

As shown in

Figure 8.

, to send this instruction to

the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.

Figure 8. Write Enable (WREN) Sequence

Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in

Figure 9.

, to send this instruction to

the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).

The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:

Power-up

WRDI instruction execution

WRSR instruction completion

WRITE instruction completion

Write Protect (W) line being held Low.

Figure 9. Write Disable (WRDI) Sequence

AI01441D

High Impedance

Instruction

AI03790D

High Impedance

Instruction

M95040, M95020, M95010

14/37

Read Status Register (RDSR)
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in

Figure 10.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Sta-
tus Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes avail-
able when a new RDSR instruction is executed, af-
ter completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.

The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in

Table 4.

) be-

comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.

Figure 10. Read Status Register (RDSR) Sequence

9 10 11 12 13 14 15

Instruction

AI01444D

Status Register Out

High Impedance

MSB

Status Register Out

MSB

15/37

M95040, M95020, M95010

Write Status Register (WRSR)
This instruction has no effect on bits b7, b6, b5, b4,
b1 and b0 of the Status Register.
As shown in

Figure 11.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and data byte are then
shifted in on Serial Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High. Chip Select (S) must be driven High
after the rising edge of Serial Clock (C) that latch-
es the eighth bit of the data byte, and before the
the next rising edge of Serial Clock (C). If this con-
dition is not met, the Write Status Register
(WRSR) instruction is not executed. The self-
timed Write Cycle starts, and continues for a peri-

od t

(as specified in

Table 18.

Table 22.

), at

the end of which the Write in Progress (WIP) bit is
reset to 0.
The instruction is not accepted, and is not execut-
ed, under the following conditions:

if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)

if a Write Cycle is already in progress

if the device has not been deselected, by Chip
Select (S) being driven High, after the eighth
bit, b0, of the data byte has been latched in

if Write Protect (W) is Low.

Figure 11. Write Status Register (WRSR) Sequence

AI01445B

9 10 11 12 13 14 15

High Impedance

Instruction

Status

MSB

M95040, M95020, M95010

16/37

Read from Memory Array (READ)
As shown in

Figure 12.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address byte are
then shifted in, on Serial Data Input (D). For the
M95040, the most significant address bit, A8, is in-
corporated as bit b3 of the instruction byte, as
shown in

Table 5.

. The address is loaded into an

internal address register, and the byte of data at
that address is shifted out, on Serial Data Output
(Q).
If Chip Select (S) continues to be driven Low, an
internal bit-pointer is automatically incremented at
each clock cycle, and the corresponding data bit is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle

to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.

Table 6. Address Range Bits

Figure 12. Read from Memory Array (READ) Sequence

Note: Depending on the memory size, as shown in

Table 6.

, the most significant address bits are Don't Care.

Device M95040

M95020

M95010

Address Bits

A8-A0

A7-A0

A6-A0

AI01440E

9 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

20 21 22

High Impedance

Data Out

Instruction

Byte Address

17/37

M95040, M95020, M95010

Write to Memory Array (WRITE)
As shown in

Figure 13.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs any-
where on the bus. In the case of

Figure 13.

, this

occurs after the eighth bit of the data byte has
been latched in, indicating that the instruction is
being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t

(as specified in

Table 18.

Table 22.

), at the end

of which the Write in Progress (WIP) bit is reset to
0.
If, though, Chip Select (S) continues to be driven
Low, as shown in

Figure 14.

, the next byte of input

data is shifted in. In this way, all the bytes from the

given address to the end of the same page can be
programmed in a single instruction.
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
The instruction is not accepted, and is not execut-
ed, under the following conditions:

if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)

if a Write cycle is already in progress

if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock
(C) that latches the last data bit, and before
the next rising edge of Serial Clock (C) occurs
anywhere on the bus)

if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block
Protect (BP1 and BP0) bits.

Figure 13. Byte Write (WRITE) Sequence

Note: Depending on the memory size, as shown in

Table 6.

, the most significant address bits are Don't Care.

AI01442D

9 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

20 21 22 23

High Impedance

Instruction

Byte Address

Data Byte

M95040, M95020, M95010

20/37

MAXIMUM RATING

Stressing the device outside the ratings listed in

Table 7.

may cause permanent damage to the de-

vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of

this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.

Table 7. Absolute Maximum Ratings

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK

7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500

, R2=500

)

Symbol

Parameter

Min.

Max.

Unit

STG

Storage Temperature

150

°C

LEAD

Lead Temperature during Soldering

See note

°C

Output Voltage

0.50

+0.6

Input Voltage

0.50

6.5

Supply Voltage

0.50

6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

4000

21/37

M95040, M95020, M95010

DC AND AC PARAMETERS

This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.

Table 8. Operating Conditions (M950x0)

Table 9. Operating Conditions (M950x0-W)

Table 10. Operating Conditions (M950x0-R)

Table 11. AC Measurement Conditions

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 15. AC Measurement I/O Waveform

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

4.5

5.5

Ambient Operating Temperature (Device Grade 6)

°C

Ambient Operating Temperature (Device Grade 3)

125

°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

2.5

5.5

Ambient Operating Temperature (Device Grade 6)

°C

Ambient Operating Temperature (Device Grade 3)

125

°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

1.8

5.5

Ambient Operating Temperature

°C

Symbol

Parameter

Min.

Max.

Unit

Load Capacitance

100

Input Rise and Fall Times

Input Pulse Voltages

0.2V

to 0.8V

Input and Output Timing Reference Voltages

0.3V

to 0.7V

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M95040, M95020, M95010

22/37

Table 12. Capacitance

Note: Sampled only, not 100% tested, at T

=25°C and a frequency of 5MHz.

Table 13. DC Characteristics (M950x0, Device Grade 6)

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.

Symbol

Parameter

Test Condition

Min

Max

Unit

OUT

Output Capacitance (Q)

OUT

= 0V

Input Capacitance (D)

= 0V

Input Capacitance (other pins)

= 0V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 5MHz,

= 5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 10MHz,

= 5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 5 V,

= V

, Previous Product

µA

S = V

, V

= 5 V,

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 2 mA, V

= 5 V

0.4

Output High Voltage

= 2 mA, V

= 5 V

0.8 V

23/37

M95040, M95020, M95010

Table 14. DC Characteristics (M950x0, Device Grade 3)

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.

Table 15. DC Characteristics (M950x0-W, Device Grade 6)

Note: 1. Previous product: identified by Process Identification letter K.

2. Present product: identified by Process Identification letter W or G.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 5 V,

= V

, Previous Product

µA

S = V

, V

= 5 V,

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 2 mA, V

= 5 V

0.4

Output High Voltage

= 2 mA, V

= 5 V

0.8 V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 2.5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 2.5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 2.5 V,

= V

, Previous Product

µA

S = V

, V

= 2.5 V

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 1.5 mA, V

= 2.5 V

0.4

Output High Voltage

= 0.4 mA, V

= 2.5 V

0.8 V

M95040, M95020, M95010

24/37

Table 16. DC Characteristics (M950x0-W, Device Grade 3)

Note: 1. Previous product: identified by Process Identification letter K.

2. Present product: identified by Process Identification letter W or G.

Table 17. DC Characteristics (M950x0-R)

Note: 1. Preliminary data: Product under development. Please contact your nearest ST sales office for information.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 2.5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 2.5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 2.5 V, V

= V

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 1.5 mA, V

= 2.5 V

0.4

Output High Voltage

= 0.4 mA, V

= 2.5 V

0.8 V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1 V

/0.9. V

at 1 MHz,

= 1.8 V, Q = open

CC1

Supply Current
(Standby Power mode)

S = V

, V

= V

, V

= 1.8 V

0.5

µA

Input Low Voltage

0.45

0.25 V

Input High Voltage

0.7 V

Output Low Voltage

= 0.15 mA, V

= 1.8 V

0.3

Output High Voltage

= 0.1 mA, V

= 1.8 V

0.8 V

25/37

M95040, M95020, M95010

Table 18. AC Characteristics (M950x0, Device Grade 6)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.

Test conditions specified in

Table 11.

and

Table 8.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

SHCH

CSS2

S Not Active Setup Time

SHSL

S Deselect Time

100

CHSH

CSH

S Active Hold Time

CHSL

S Not Active Hold Time

CLH

Clock High Time

CLL

Clock Low Time

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

HLCH

Clock Low Hold Time after HOLD Active

CHHL

Clock High Set-up Time before HOLD Active

CHHH

Clock High Set-up Time before HOLD not Active

SHQZ

DIS

Output Disable Time

100

CLQV

Clock Low to Output Valid

CLQX

Output Hold Time

QLQH

Output Rise Time

QHQL

Output Fall Time

HHQV

HOLD High to Output Valid

HLQZ

HOLD Low to Output High-Z

100

Write Time

M95040, M95020, M95010

26/37

Table 19. AC Characteristics (M950x0, Device Grade 3)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 11.

and

Table 8.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CHHL

Clock High Set-up Time before HOLD Active

CHHH

Clock High Set-up Time before HOLD not
Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

27/37

M95040, M95020, M95010

Table 20. AC Characteristics (M950x0-W, Device Grade 6)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 11.

and

Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CHHL

Clock High Set-up Time before HOLD Active

CHHH

Clock High Set-up Time before HOLD not Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

M95040, M95020, M95010

28/37

Table 21. AC Characteristics (M950x0-W, Device Grade 3)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 11.

and

Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CHHL

Clock High Set-up Time before HOLD Active

CHHH

Clock High Set-up Time before HOLD not
Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

29/37

M95040, M95020, M95010

Table 22. AC Characteristics (M950x0-R)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data: Product under development. Please contact your nearest ST sales office for information.

Test conditions specified in

Table 11.

and

Table 10.

Symbol

Alt.

Parameter

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CHHL

Clock High Set-up Time before HOLD Active

120

CHHH

Clock High Set-up Time before HOLD not Active

120

SHQZ

DIS

Output Disable Time

250

CLQV

Clock Low to Output Valid

180

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

Write Time

35/37

M95040, M95020, M95010

PART NUMBERING

Table 26. Ordering Information Scheme

Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-

tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

2. Used only for Device Grade 3

For a list of available options (speed, package,
etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-
fice.

Table 27. How to Identify Present and Previous Products by the Process Identification Letter

Example:

M95040

W MN

Device Type

M95 = SPI serial access EEPROM

Device Function
040 = 4 Kbit (512 x 8)

020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)

Operating Voltage

blank = V

= 4.5 to 5.5V

W = V

= 2.5 to 5.5V

R = V

= 1.8 to 5.5V

Package
BN = PDIP8

MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)

Device Grade

6 = Industrial temperature range, 40 to 85 °C.
Device tested with standard test flow

3 = Device tested with High Reliability Certified Flow

Automotive temperature range (40 to 125 °C)

Option

blank = Standard Packing
T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb

-free and TBBA-free

Process

blank = F6SP20%
/W = F6SP36%

Markings on Present Products

Markings on Previous Products

95040W6

AYWWW (or AYWWG)

95040W6

AYWWK

M95040, M95020, M95010

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REVISION HISTORY

Table 28. Document Revision History

Date

Version

Description of Revision

10-May-2000

2.2

s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation

16-Mar-2001

2.3

Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab
9. Wording changes, according to the standard glossary
Illustrations and Package Mechanical data updated

19-Jul-2001

2.4

Temperature range `3' added to the -W supply voltage range in DC and AC characteristics

11-Oct-2001

3.0

Document reformatted using the new template

26-Feb-2002

3.1

Description of chip deselect after 8th clock pulse made more explicit

27-Sep-2002

3.2

Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance C

changed

24-Oct-2002

3.3

Minimum values for tCHHL and tCHHH changed.

24-Feb-2003

3.4

Description of Read from Memory Array (READ) instruction corrected, and clarified

28-May-2003

3.5

New products, identified by the process letter W, added

25-Jun-2003

3.6

Correction to current products, identified by the process letter K not L.
I

changed in DC characteristics, and t

CHHL

, t

CHHH

substituted in AC characteristics

Voltage range -S upgraded by removing it, and adding the -R voltage range in its place
Temperature range 5 removed.

21-Nov-2003

4.0

Table of contents, and Pb-free options added. V

(min) improved to -0.45V

02-Feb-2004

4.1

(max) and t

CLQV

(max) changed

01-Mar-2004

5.0

Absolute Maximum Ratings for V

(min) and V

(min) improved. Soldering temperature

information clarified for RoHS compliant devices. New 5V and 2.5V devices, with process
letter W, promoted from preliminary data to full data. Device Grade 3 clarified, with reference
to HRCF and automotive environments

05-Oct-2004

6.0

Product List summary table added. Process identification letter "G" information added. Order
information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade
informaton clarified. tHHQX corrected to tHHQV. Signal Description updated.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified

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M95040, M95020, M95010

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M95010-DW3T

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M95010-DW3T