PRELIMINARY DATA

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

January 2006

Rev1.0

1/23

NAND01G-N

1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and

512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package

Features summary

Multi-chip Package

NAND Flash Memory

512 Mbit or 1 Gbit (x8/x16) Large Page

Size NAND Flash Memory

512 Mbit (x16) SDR or DDR LPSDRAM

Temperature range

-30 up to 85 °C

Supply voltage

NAND Flash : V

DDF

= 1.7V to 1.95V

LPSDRAM: V

DDD

= V

DDQD

= 1.7V to 1.9V

Electronic Signature

ECOPACK

packages

Flash Memory

Nand Interface

x8 or x16 bus width

Multiplexed address/data

Page size

x8 device: (2048 + 64 spare) Bytes

x16 device: (1024 + 32 spare) Words

Block size

x8 device: (128K + 4K spare) Bytes

x16 device: (64K + 2K spare) Words

Page Read/Program

Random access: 25µs (max)

Sequential access: 50ns (min)

Page program time: 300µs (typ)

Copy Back Program mode

Fast page copy without external buffering

Fast Block Erase

Block Erase time: 2ms (typ)

Chip Enable `don't care'

for simple interfacing with microcontrollers

Status Register

SDR/DDR LPSDRAM

Interface: x16 bus width

Programmable Partial Array Self Refresh

Auto Temperature Compensated Self Refresh

Deep Power Down mode

1.8V LVCMOS interface

Quad internal Banks controlled by BA0 and
BA1

Wrap sequence: Sequential/Interleaved

Automatic and Controlled Precharge

Auto Refresh and Self Refresh

8,192 Refresh Cycles/64ms

Burst Termination by Burst Stop command and
Precharge Command

FBGA

TFBGA107 10.5 x 13 x 1.2mm
TFBGA149 10 x 13.5 x 1.2mm

www.st.com

NAND01G-N

Contents

Rev1.0

3/23

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

NAND Flash component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

LPSDRAM component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1

Flash memory Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2

Flash memory Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . 12

2.3

Flash memory Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . 12

2.4

Flash memory Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . 12

2.5

Flash memory Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6

Flash memory Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.7

Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.8

Flash memory Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.9

Flash memory Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10

Flash memory V

DDF

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.11

Flash memory V

SSF

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.12

LPSDRAM Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.13

LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 14

2.14

LPSDRAM Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . 14

2.15

LPSDRAM Chip Select (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.16

LPSDRAM Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . 14

2.17

LPSDRAM Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.18

LPSDRAM Write Enable (WD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.19

LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.20

LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.21

LPSDRAM Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.22

LPSDRAM Lower/Upper Data Input/Output Mask (DQM0, DQM1) . . . . . 15

2.23

Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . 15

2.24

LPSDRAM V

DDD

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.25

LPSDRAM V

DDQD

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.26

LPSDRAM V

SSD

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

NAND01G-N

List of tables

Rev1.0

5/23

List of tables

Table 1.

Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2.

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4.

TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data . . . . . . 19

Table 5.

TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data . . . . . . 20

Table 6.

Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7.

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

List of figures

NAND01G-N

6/23

Rev1.0

List of figures

Figure 1.

Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.

TFBGA107 connections, x16 Bus Width (Top view through package) . . . . . . . . . . . . . . . . 10

Figure 3.

TFBGA149 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5.

TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline . . . . . . 19

Figure 6.

TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline . . . . . . 20

NAND01G-N

Summary description

Rev1.0

7/23

1 Summary

description

The NAND01G-N is a family that combine two memory devices in a Multi-Chip Package: a 1
Gbit NAND Flash memory and 512 Mbit LPSDRAM with 2Kbyte Pages.

The NAND Flash memory and LPSDRAM components have separate power supplies and
grounds. They also have separate control, address and input/output signals, which allows
simultaneous access to both devices at any moment.

They are distinguished by two Chip Enable inputs: E

for the NAND Flash memory and E

for the LPSDRAM.

The Multi-Chip Packages are available with a 1.8V supply. See

Table 1

for a complete list of

the products available.

All devices are stacked and are offered in:

TFBGA107 (10.5 x 13 x 1.2mm)

TFBGA149 (10 x 13.5 x 1.2mm)

They are supplied with all the NAND Flash memory bits erased (set to `1').

This datasheet should be read in conjunction with the NAND Flash and LPSDRAM
datasheets.

NAND Flash component

NAND01G-N devices contain a 1 Gbit (x8/x16) 2112 Byte/1056 Word Page, NAND Flash
Memory. For detailed information on how to use the devices, see the NANDxxx-B datasheet
which is available from your local STMicroelectronics distributor.

LPSDRAM component

NAND01G-N devices contain a 512 Mbit (x16) LPSDRAM. For detailed information on how
to use the devices, see:

M65KA512AB: SDR 512Mb (x16)

M65KG512AB: DDR 512Mb (x16)

All above ST datasheets available from ST divisional Marketing.

NAND01G-N

Summary description

Rev1.0

9/23

Table 2.

Signal Names

NAND Flash memory

I/O0-I/O7

Data Input/Outputs for x8 and x16 devices

I/O8-I/O15

Data Inputs/Outputs for x16 devices

Address Latch Enable

Command Latch Enable

Chip Enable

Read Enable

Ready/Busy (open-drain output)

Write Enable

Write Protect

DDF

Supply Voltage

SSF

Ground

LPSDRAM

A0-A12

Address Inputs

A10 determines the Precharge mode.

BA0-BA1

Bank Select Inputs

DQ0-DQ15

Data Inputs/Outputs

UDQS-LDQS

(1)

Available on NAND01GR4N5 only.

Data Strobe Inputs/Outputs

Clock Input

(1)

Clock Input

Clock Enable Input

Chip Select inputs

Write Enable Input

RAS

Row Address Strobe Input

CAS

Column Address Strobe Input

DQM0

DQ Mask Enable Input (controls DQ0-DQ7)

DQM1

DQ Mask Enable Input (controls DQ8-DQ15)

DDD

Supply Voltage

DDQD

Input/Output Supply Voltage

SSD

Ground

SSQD

Input/Output Ground

Not Connected Internally

Do Not Use

Summary description

NAND01G-N

10/23

Rev1.0

Figure 2.

TFBGA107 connections, x16 Bus Width (Top view through package)

AI10143c

VDDD

DQM1

VSSD

A12

DQM0

DQ4

VSSD

VDDQD

BA0

DQ6

VSSQD

CAS

A11

BA1

A10

VDDD

VSSD

DQ15

DQ11

I/O6

VDDQD

VSSQD

DQ9

I/O5

DQ13

VDDD

VSSF

VDDF

I/O4

I/O7

VSSQD

DQ2

I/O3

VDDF

I/O2

DQ0

VSSF

I/O1

VSSD

I/O0

DQ1

DQ3

DQ5

DQ7

VDDD

DQ10

DQ12

DQ14

VSSF

DQ8

RAS

VDDF

NAND01G-N

Summary description

Rev1.0

11/23

Figure 3.

TFBGA149 Connections (Top view through package)

AI11007c

DQM1

A11

DQM0

DQ4

BA0

DQ6

CAS

BA1

VDDD

DQ15

DQ13

VSSF

I/O0

I/O7

VSSQD

DQ2

I/O2

DQ0

VSSD

I/O1

DQ1

DQ3

DQ5

DQ7

VDDD

DQ10

VSSD

DQ8

RAS

VDDF

A10

VDDQD

VSSD

VDDD

I/O6

I/O5

A12

I/O4

VDDF

VSSF

I/O3

DQ11

DQ14

DQ12

DQ9

VDDQD

VSSD

I/O9

I/O8

I/O15

I/O14

I/O13

I/O10

I/O12

I/O11

LDQS

UDQS

Signals description

NAND01G-N

12/23

Rev1.0

2 Signals

description

See

Figure 1

in conjunction with

Table 2

, for a brief overview of the signals connected to this

device.

For extra details on the signals, refer to the NAND Flash and the LPSDRAM datasheets.

2.1

Flash memory Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used by the NAND Flash memory to input the selected address,
output the data during a Read operation or input a command or data during a Write
operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left
floating when the NAND Flash memory is deselected or the outputs are disabled.

2.2

Flash memory Inputs/Outputs (I/O8-I/O15)

Input/Outputs 8 to 15 are only available in x16 NAND Flash devices. They are used to output
the data during a Read operation or input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.

2.3

Flash memory Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command
Interface of the NAND Flash memory. When AL is high, the inputs are latched on the rising
edge of Write Enable.

2.4

Flash memory Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command
Interface of the NAND Flash memory. When CL is high, the inputs are latched on the rising
edge of Write Enable.

2.5

Flash memory Chip Enable (E

)

The NAND Flash memory Chip Enable input activates the memory control logic, input
buffers, decoders and sense amplifiers. When Chip Enable is low, V

, the NAND Flash

memory device is selected. If Chip Enable goes high, v

, while the NAND Flash memory is

busy, the device remains selected and does not go into standby mode.

NAND01G-N

Signals description

Rev1.0

13/23

2.6

Flash memory Read Enable (R)

The NAND Flash memory Read Enable pin, R, controls the sequential data output during
Read operations. The falling edge of R also increments the internal column address counter
by one.

2.7

Flash memory Write Enable (W

)

The NAND Flash memory Write Enable input, W, controls writing to the Command Interface,
Input Address and Data latches. Both addresses and data are latched on the rising edge of
Write Enable.

2.8

Flash memory Write Protect (WP)

The Write Protect pin is a NAND Flash memory input that gives a hardware protection
against unwanted program or erase operations. When Write Protect is Low, V

, the NAND

Flash memory device does not accept any program or erase operations.

It is recommended to keep the Write Protect pin Low, V

, during power-up and power-down.

2.9

Flash memory Ready/Busy (RB)

The Ready/Busy output, RB, is an open-drain NAND Flash memory output that can be used
to identify if the P/E/R Controller is currently active.

When Ready/Busy is Low, V

, a read, program or erase operation is in progress. When the

operation completes Ready/Busy goes High, V

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

2.10

Flash memory V

DDF

supply voltage

DDF

provides the power supply to the internal core of the NAND Flash memory device. It is

the main power supply for all operations (read, program and erase).

2.11

Flash memory V

SSF

ground

Ground, V

SSF,

is the reference for the power supply for the NAND Flash memory. It must be

connected to the system ground.

Signals description

NAND01G-N

14/23

Rev1.0

2.12

LPSDRAM Address Inputs (A0-A12)

The A0-A12 Address Inputs are used by the LPSDRAM to select the row or column to be
made active. If a row is selected, all thirteen, A0-A12 Address Inputs are used. If a column is
selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case,
A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or
Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to
`0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.

2.13

LPSDRAM Bank Select Address Inputs (BA0-BA1)

The BA0 and BA1 Banks Select Address Inputs are used by the LPSDRAM to select the
bank to be made active.

The LPSDRAM must be enabled, the Row Address Strobe, RAS, must be Low, V

, the

Column Address Strobe, CAS, and W must be High, V

, when selecting the addresses.

2.14

LPSDRAM Data Inputs/Outputs (DQ0-DQ15)

On the LPSDRAM, DQ0-DQ15 output the data stored at the selected address during a
Read operation, or are used to input the data during a write operation.

2.15

LPSDRAM Chip Select (E

)

The Chip Select input E activates the LPSDRAM state machine, address buffers and
decoders when driven Low, V

. When High, V

the device is not selected.

2.16

LPSDRAM Column Address Strobe (CAS)

The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and
BA1-BA0, to select the starting column location prior to a Read or Write.

2.17

LPSDRAM Row Address Strobe (RAS)

The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and
BA1-BA0, to select the starting address location prior to a Read or Write.

2.18

LPSDRAM Write Enable (W

)

The LPSDRAM Write Enable input, W, controls writing to the LPSDRAM.

NAND01G-N

Signals description

Rev1.0

15/23

2.19

LPSDRAM Clock Input (K)

The Clock signal, K, is used to clock the Read and Write cycles on the LPSDRAM. During
normal operation, the Clock Enable pin, KE, is High, V

. The clock signal K can be

suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down
mode by driving KE Low, V

2.20

LPSDRAM Clock Input (K)

The Clock signal, K, is only available on the DDR LPSDRAM. It is used in conjunction with
the Clock signal, K.

All LPSDRAM input signals except DQM0/DQM1, UDQS/LDQS and DQ0-DQ15 are
referred to the cross point of K rising edge and K falling edge.

2.21

LPSDRAM Clock Enable (KE)

The Clock Enable, KE, pin is used by the LPSDRAM to control the synchronizing of the
signals with Clock signal K (and K on DDR LPSDRAM). If KE is High, V

, the next Clock

rising edge is valid. When KE is Low, V

, the signals are no longer clocked and data Read

and Write cycles are extended. KE is also involved in switching the device to the Self-
Refresh, Power-Down and Deep Power-Down modes.

2.22

LPSDRAM Lower/Upper Data Input/Output Mask (DQM0,
DQM1)

Data Mask Enable Inputs are used to mask the Read or Write data.

2.23

Lower/Upper Data Read/Write Strobe Input/Output (LDQS,
UDQS)

LDQS and UDQS are only available on the DDR LPSDRAM. They can be either input or
output signals and act as write data strobe and read data strobe respectively. LDQS and
UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15, respectively.

2.24 LPSDRAM

DDD

supply voltage

DDD

provides the power supply to the internal core of the LPSDRAM. It is the main power

supply for all operations (Read and Write).

NAND01G-N

Functional description

Rev1.0

17/23

3 Functional

description

The NAND Flash memory and LPSDRAM components have separate power supplies and
grounds. They also have separate control signals, addresses and data input/outputs, which
allows simultaneous access to both devices at any moment.

Figure 4.

Functional Block Diagram

Available on Root Part Number 2 only.

SSD

1 Gbit

NAND Flash

Memory

DDF

CAS

RAS

LPSDRAM

DDD

DQM0

DQM1

BA0-BA1

Ai12401

I/O0-I/O7

I/O8-I/O15

SSF

DDQD

A0-A12

K(1)

SSQD

DQ0-DQ15

LDQS-UDQS (1)

Maximum rating

NAND01G-N

18/23

Rev1.0

4 Maximum

rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 3.

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Min

Max

Ambient Operating Temperature

-30

°C

BIAS

Temperature Under Bias

(1)

TBD

°C

STG

Storage Temperature

-55

125

°C

NAND Flash Input or Output Voltage

1.8V

-0.6

2.7

LPSDRAM Input or Output Voltage

1.8V

-1.0

2.6

DDF

NAND Flash Supply Voltage

1.8V

-0.6

2.7

DDD

, V

DDQD

LPSDRAM Supply Voltage

1.8V

-1.0

2.6

LPSDRAM Short Circuit

Output Current

LPSDRAM Power

Dissipation

TBD stands for `To Be Determined'.

NAND01G-N

Package mechanical

Rev1.0

19/23

5 Package

mechanical

Figure 5.

TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline

BGA-Z24

ddd

BALL "B1"

Table 4.

TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data

Symbol

millimeters

inches

Typ

Min

Max

Typ

Min

Max

1.20

0.047

0.25

0.010

0.80

0.031

0.45

0.40

0.50

0.018

0.016

0.020

10.50

10.40

10.60

0.413

0.409

0.417

7.20

0.283

ddd

0.10

0.004

13.00

12.90

13.10

0.512

0.508

0.516

10.40

0.409

0.80

0.031

1.65

0.065

1.30

0.051

0.40

0.016

0.40

0.016

Package mechanical

NAND01G-N

20/23

Rev1.0

Figure 6.

TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline

Drawing not to scale.

BGA-Z78

ddd

BALL "A1"

Table 5.

TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data

Symbol

millimeters

inches

Typ

Min

Max

Typ

Min

Max

1.200

0.0472

0.250

0.0098

0.800

0.0315

0.450

0.400

0.500

0.0177

0.0157

0.0197

10.000

9.900

10.100

0.3937

0.3898

0.3976

8.800

0.3465

ddd

0.100

0.0039

13.500

13.400

13.600

0.5315

0.5276

0.5354

12.000

0.4724

0.800

0.0315

0.600

0.0236

0.750

0.0295

0.400

0.0157

0.400

0.0157

NAND01G-N

Part numbering

Rev1.0

21/23

6 Part

numbering

Devices are shipped from the factory with the Flash memory content bits, in valid blocks,
erased to '1'. For further information on any aspect of this device, please contact your
nearest ST Sales Office.

Table 6.

Ordering Information Scheme

Example:

NAND01G R

Device Type

NAND Flash Memory

NAND Flash Density

01G = 1Gb

NAND Flash Operating Voltage

R = 1.7V to 1.95V

Bus Width

3 = x8

4 = x16

Family Identifier

N = 2112 Byte Page NAND Flash + LPSDRAM

Device Options

5 = DDR LPSDRAM 512Mbit (x16), 133 Mhz, BGA149

6 = SDR LPSDRAM 512Mbit (x 16), 133Mhz, BGA107

Product Version

Package

ZB = TFBGA

ZC = LFBGA

Reserved

Option

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Revision history

NAND01G-N

22/23

Rev1.0

7 Revision

history

Table 7.

Document Revision History

Date

Version

Revision Details

18-Oct-2004

0.1

First Issue

19-Oct-2004

0.2

Figure 1: Logic Diagram

modified.

Table 1: Product List

modified.

26-Oct-2005

0.3

NAND512-N device removed from the document.TFBGA137 packages
removed from document. SDR 256Mb (x32) and SDR 512Mb (x32)
devices removed from document. NAND01GR3N3 removed throughout
document.

LDQM and UDQM replaced respectively by DQM0 and DQM1throughout
document.

DRAM changed to LPSDRAM throughout document.

LFBGA107 added throughout document. NAND01GR3N1,
NAND01GR3N2, NAND01GR3N6, NAND01GR4N5 added throughout
document.

31-Jan-2006

1.0

Note 1 below

Table 2: Signal Names

and

Figure 1: Logic Diagram

added

to cover both part numbers.

Figure 2: TFBGA107 connections, x16 Bus Width (Top view through
package)

and

Figure 3: TFBGA149 Connections (Top view through

package)

updated.

Section 2: Signals description

and

Section 3: Functional description

added.

256Mb LPSDRAM removed.

LFBGA107 (12 x 13 x 1.4mm) and LFBGA149 (10 x 13.5 x 1.4mm)
replaced by TFBGA107 (10.5x13x1.2mm) and TFBGA149
(10x13.5x1.2mm), respectively.

NAND01G-N

23/23

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NAND01GR4N5

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NAND01GR4N5